ARINC 429 Bus Interface - Actel
– Structural VHDL and Verilog Netlists † RTL version – VHDL or Verilog Core Source Code – Synthesis Scripts † Verification Testbench – Verilog † User Testbenches – Libero IDE Compatible – VHDL and Verilog Development System † Complete ARINC 429 Rx/Tx † Implementation – Implemented in an APA600 Device
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