SPARC V8 32-bit Processor LEON3 / LEON3-FT …

1 Copyright Aeroflex Gaisler ABMarch 2010, Version V8 32-bit ProcessorLEON3 / LEON3 -FTCompanionCore Data Sheet GAISLERF eatures SPARC V8 integer unit with 7-stage pipeline Hardware multiply, divide and MAC units Separate instruction and data caches Support for 2 - 32 register windows Radix-2 divider (non-restoring) Single-vector trapping for reduced code size Advanced debug support unit Optional IEEE-STD-754 compliant FPU 20 DMIPS at 25 MHz system clock Fault-tolerant version available Support for Fusion, IGLOO, ProASIC3E/L, RT ProASIC3, Axcelerator and RTAXD escriptionThe LEON3 is a 32-bit Processor based on theSPARC V8 architecture.

2 It implements a 7-stagepipeline and separate instruction and data caches(Harvard architecture). The number of registerwindows is configurable within the limit of theSPARC standard. A unique debug interfaceallows non-intrusive hardware debugging andprovides access to all registers and LEON3 Processor is designed for embeddedapplications, combining high performance withlow complexity and low power LEON3 Processor is highly fault-tolerant version of the LEON3processor in combination with the radiationtolerant Actel RTAX FPGA gives a totalimmunity to radiation effects.

3 This makes itideally suited for space and other Register FileAMBA AHB Master ( 32-bit )AHB I/FLEON3 Interrupt controllerCo-ProcessorHW MUL/DIVIEEE-754 FPUT race BufferDebug portInterrupt portDebug support unitLocal DRAML ocal IRAMSRMMUDTLBITLB7-StageInteger Pipeline2 LEON3 / LEON3 -FTCopyright Aeroflex Gaisler ABMarch 2010, Version LEON3 SPARC V8 Processor core has been designed to fit into architectures from which a largevariety of applications can be derived. The LEON3 SPARC V8 Processor core can be combined with the IEEE-STD-754 compliant FloatingPoint Unit (GRFPU Lite).

4 The architecture is centered around the AMBA Advanced High-speed Bus (AHB), to which theLEON3 core and other high-bandwidth units are connected. Low-bandwidth units connected to theAMBA Advanced Peripheral Bus (APB) which is accessed through an AHB to APB bridge. Thearchitecture is shown in figure 1. Architectural block diagram of a typical system using the LEON3 processorLEON3FT32-bit SPARCI nteger EDACSDRAMC ontrollerwith EDACS paceWireCodecInterfaceMil-Std-1553BC/RT/ MTInterface2 x UART16 x GPIOMil-Std-1553 RTInterface32-bit AMBA AHBT imersInterruptAHB / APBUARTD ebugLinkJTAGD ebugLinkOn-ChipMemorywith EDACFPUPROM/SRAMSDRAMLVDS / LEON3 -FTCopyright Aeroflex Gaisler ABMarch 2010, Version overviewThe LEON3 signals are shown in figure 2.

5 Note that the AMBA AHB and debug signals are imple-mented VHDL records and are not shown in detail. characteristicsThe LEON3 Processor is inherently portable and can be implemented on most FPGA and ASIC tech-nologies. Table 1 shows the approximate cell count and frequency for different example configura-tions on Actel RTAX and RT ProASIC3, with 8 kbyte instruction and 4 kbyte data LEON3 core is available in VHDL source code or as a pre-synthesized netlist. The LEON3 -FT core is available as a pre-synthesized netlist characteristics (Cells / RAM blocks / AHB MHz)Core configurationRTAX2000S-1RT ProASIC3RT ProASIC3 with TMRLEON36500 / 31 / 25 MHz-- LEON3 + GRFPU Lite13500 / 35 / 20 MHz-- LEON3 -FT7500 / 31 / 25 MHz8400 / 39 / 25 MHz12300 / 39 / 25 MHzLEON3-FT + GRFPU-FT Lite14600 / 35 / 20 MHz18200 / 47 / 20 MHz24800 / 47 / 20 MHzFigure 2.

6 Signal [3:0] [3:0] & ResetdbgiahboahbiahbsiAMBAD ebug4 LEON3 / LEON3 -FTCopyright Aeroflex Gaisler ABMarch 2010, Version GAISLER2 LEON3 - High-performance SPARC V8 32-bit is a 32-bit Processor core conforming to the IEEE-1754 ( SPARC V8) architecture. It isdesigned for embedded applications, combining high performance with low complexity and lowpower consumption. The LEON3 core has the following main features: 7-stage pipeline with Harvard architecture, sepa-rate instruction and data caches, hardware multiplier and divider, on-chip debug support and multi- Processor extensions.

7 Note: this manual describes the full functionality of the LEON3 core. Through the use of VHDL generics, parts of the described functionality can be suppressed or modified to generate a smaller orfaster unitThe LEON3 integer unit implements the full SPARC V8 standard, including hardware multiply anddivide instructions. The number of register windows is configurable within the limit of the SPARC standard (2 - 32), with a default setting of 8. The pipeline consists of 7 stages with a separate instruc-tion and data cache interface (Harvard architecture).

8 Sub-systemLEON3 has a highly configurable cache system, consisting of a separate instruction and data caches can be configured with 1 - 4 sets, 1 - 256 kbyte/set, 16 or 32 bytes per line. Sub-blockingis implemented with one valid bit per 32-bit word. The instruction cache uses streaming during line-refill to minimize refill latency. The data cache uses write-through policy and implements a double-word write-buffer. The data cache can also perform bus-snooping on the AHB bus. A local scratchInteger pipelineI-CacheD-Cache3-Port Register FileAMBA AHB Master ( 32-bit )AHB I/F7-StageInterrupt controllerCo-ProcessorHW MUL/DIVIEEE-754 FPUT race BufferDebug portInterrupt portDebug support unitLocal DRAML ocal IRAMF igure 3.

9 LEON3 Processor core block diagramSRMMUDTLBITLB5 LEON3 / LEON3 -FTCopyright Aeroflex Gaisler ABMarch 2010, Version GAISLERpad ram can be added to both the instruction and data cache controllers to allow 0-waitstates accessmemory without data write unit and co-processorThe LEON3 integer unit provides interfaces for a floating-point unit (FPU), and a custom co-proces-sor. Two FPU controllers are available, one for the high-performance GRFPU (available from GaislerResearch) and one for the Meiko FPU core (available from Sun Microsystems).

10 The floating-pointprocessors and co- Processor execute in parallel with the integer unit, and does not block the operationunless a data or resource dependency management unitA SPARC V8 Reference Memory Management Unit (SRMMU) can optionally be enabled. TheSRMMU implements the full SPARC V8 MMU specification, and provides mapping between multi-ple 32-bit virtual address spaces and 36-bit physical memory. A three-level hardware table-walk isimplemented, and the MMU can be configured to up to 64 fully associative TLB debug supportThe LEON3 pipeline includes functionality to allow non-intrusive debugging on target hardware.