AXI DataMover v5 - Xilinx
data transport and protocol conversion. The function is intended to be a standalone core for custom designs. Features • AXI4 Compliant • Primary AXI4 data width support of 32, 64, 128, 256, 512, and 1,024 bits • Primary AXI4-Stream data width support of 8, 16, 32, 64, 128, 256, 512 and 1,024 bits • Parameterized Memory Map Burst Lengths
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