AXI GPIO v2 - Xilinx
Channel 1 general purpose output pins. Width of this port is configurable based on GPIO Width. gpio_io_t(4) GPIO O 1 Channel 1 general purpose 3-state pins. Width of this port is configurable based on GPIO Width. gpio2_io_i(1)(3) GPIO I Channel 2 general purpose input pins. Width of this port is configurable based on GPIO2 Width.
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