AXI Interconnect v2 - Xilinx
AXI Interconnect Product Guide v2.1 7 PG059 December 20, 2017 www.xilinx.com Chapter 1:Overview ° Configurable Write and Read transaction issuing limits for each connected slave. ° Optional single-thread mode (per connected master) reduces thread control logic by allowing one or more outstanding transactions from only one thread ID at a time.
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