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AXI Interconnect v2 - Xilinx

AXI Interconnect v2 - Xilinx

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The Xilinx® LogiCOREIP AXI Interconnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. Note:The AXI Interconnect core is intended for memory-mapped transfers only. For AXI4-Stream transfers, see the AXI4-Stream Infrastructure IP Suite LogiCORE IP Product Guide (PG085) [Ref1]. Features

  Memory, Xilinx, Logicore, Logicore ip

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