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AXI Interrupt Controller (INTC) v4 - Xilinx

AXI Interrupt Controller (INTC) v4 - Xilinx

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IAR SIE 1 CIE 1 IVR MER Int Det Irq Gen 1 IMR ILR1 IVAR 1 ... intended for inter-processor interrupts in multi-processor systems. These interrupts are triggered by software writing to the Interrupt Status Register. Nested Interrupts The core provides support for nested interrupts, by implementing an Interrupt Level ...

  System, Xilinx

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