AXI UART Lite v2 - Xilinx
The AXI UART Lite resource ut ilization for various parameter co mbinations measured with a 7 series device. Note: Resource numbers for UltraScale architecture-based devices and Zynq devices are expected to be similar to 7 series device numbers. Port Descriptions The AXI UART Lite I/O signals are listed and described in Table 2-3.
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