I2C bus specifications - CERN
The lpGBT I2C master interface is the only master interface permitted to connect on the bus. All front-end ASICs; namely the MPA, the SSA, the CiC, the CBC, must implement an I2C Slave interface. Generation of clock signals on the I2C-bus is always the responsibility of the master device. Figure 1 I2C Bus topology for PS and 2S modules.
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