Example: air traffic controller
Search results with tag "I2c master"
MCP2221 USB 2.0 to I2C/UART Protocol Converter with GPIO
ww1.microchip.comI2C/SMBus • The Device Runs as an I2C Master. The Data to Write/Read on the I2C Bus is Conveyed by the USB Interface •I2C Master - Up to 400 kHz Clock Rate - Supports 7-Bit or 10-Bit Addressable Devices; 10-Bit Addressable Devices are Supported through the PC Host Library - Supports Block Reads/Writes of up to 65,535 Bytes • SMBus Master
I2C bus specifications - CERN
espace.cern.chThe I2C Bus Topology for the PS and 2S is shown in Figure 1. The optical link communication ASIC; namely the lpGBT (low power GigaBit Transceiver) is equipped with two independent I2C master interfaces that realize two independent I2C busses. The lpGBT I2C master interface is the only master interface permitted to connect on the bus.