Interrupts) - RISC-V
Jul 12, 2016 · 30 1.9draft: Volume II: RISC-V Privileged Architectures XLEN-1 12 11 10 9 8 7 6 5 4 3 2 1 0 WPRI MEIE HEIE SEIE UEIE MTIE HTIE STIE UTIE MSIE HSIE SSIE USIE XLEN-12 1 1 1 1 1 1 1 1 1 1 1 1 Figure 3.11: Machine interrupt-enable register (mie). HTIP bits may be written by M-mode software to deliver timer interrupts to lower privilege levels.
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