The RISC-V Instruction Set Manual, Volume I: User- Level ...

1 The RISC-V Instruction Set manual , Volume I: user - Level ISA, Version WatermanYunsup LeeDavid A. PattersonKrste AsanovicElectrical Engineering and Computer SciencesUniversity of California at BerkeleyTechnical Report No. UCB/EECS-2014-54 6, 2014 Copyright 2014, by the author(s).All rights reserved. Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and that copiesbear this notice and the full citation on the first page. To copy otherwise, torepublish, to post on servers or to redistribute to lists, requires prior RISC-V Instruction Set ManualVolume I: user - Level ISAV ersion Waterman, Yunsup Lee, David Patterson, Krste Asanovi cCS Division, EECS Department, University of California, 6, 2014 PrefaceThis is the second release of the user ISA specification, and we intend the specification of thebase user ISA plus general extensions ( , IMAFD) to remain fixed for future development.

2 Thefollowing changes have been made since Version [25] of this ISA specification. The ISA has been divided into an integer base with several standard extensions. The Instruction formats have been rearranged to make immediate encoding more efficient. The base ISA has been defined to have a little-endian memory system, with big-endian orbi-endian as non-standard variants. Load-Reserved/Store-Conditional (LR/SC) instructions have been added in the atomic in-struction extension. AMOs and LR/SC can support the release consistency model. The FENCE Instruction provides finer-grain memory and I/O orderings. An AMO for fetch-and-XOR (AMOXOR) has been added, and the encoding for AMOSWAPhas been changed to make room. The AUIPC Instruction , which adds a 20-bit upper immediate to the PC, replaces the RDNPC Instruction , which only read the current PC value.

3 This results in significant savings forposition-independent code. The JAL Instruction has now moved to the U-Type format with an explicit destinationregister, and the J Instruction has been dropped being replaced by JAL withrd=x0. Thisremoves the only Instruction with an implicit destination register and removes the J-Typeinstruction format from the base ISA. There is an accompanying reduction in JAL reach, buta significant reduction in base ISA complexity. The static hints on the JALR Instruction have been dropped. The hints are redundant withtherdandrs1register specifiers for code compliant with the standard calling convention. The JALR Instruction now clears the lowest bit of the calculated target address, to simplifyhardware and to allow auxiliary information to be stored in function pointers. The and instructions have been renamed to and ,respectively.

4 Similarly, and instructions have been renamed to , respectively. The MFFSR and MTFSR instructions have been renamed to FRCSR and FSCSR, respec-tively. FRRM, FSRM, FRFLAGS, and FSFLAGS instructions have been added to individu-ally access the rounding mode and exception flags subfields of thefcsr. The and instructions now source their operands fromrs1, instead change simplifies datapath design. and floating-point classify instructions have been I: RISC-V user - Level ISA A simpler NaN generation and propagation scheme has been adopted. For RV32I, the system performance counters have been extended to 64-bits wide, with separateread access to the upper and lower 32 bits. Canonical NOP and MV encodings have been defined. Standard Instruction -length encodings have been defined for 48-bit, 64-bit, and>64-bit in-structions. Description of a 128-bit address space variant, RV128, has been added.

5 Major opcodes in the 32-bit base Instruction format have been allocated for User- definedcustom extensions. A typographical error that suggested that stores source their data fromrdhas been correctedto refer RISC-V ISA Overview .. Instruction Length Encoding .. Exceptions, Traps, and Interrupts ..62 RV32I Base Integer Instruction Programmers Model for Base Integer Subset .. Base Instruction Formats .. Immediate Encoding Variants .. Integer Computational instructions .. Control Transfer instructions .. Load and Store instructions .. Memory Model .. System instructions .. 213 RV64I Base Integer Instruction Register State .. Integer Computational instructions .. Load and Store instructions .. System instructions .. 26iiiivVolume I: RISC-V user - Level ISA M Standard Extension for Integer Multiplication and Multiplication Operations.

6 Division Operations .. 285 A Standard Extension for Atomic Specifying Ordering of Atomic instructions .. Load-Reserved/Store-Conditional instructions .. Atomic Memory Operations .. 326 F Standard Extension for Single-Precision F Register State .. Floating-Point Control and Status Register .. NaN Generation and Propagation .. Single-Precision Load and Store instructions .. Single-Precision Floating-Point Computational instructions .. Single-Precision Floating-Point Conversion and Move instructions .. Single-Precision Floating-Point Compare instructions .. Single-Precision Floating-Point Classify Instruction .. 427 D Standard Extension for Double-Precision D Register State .. Double-Precision Load and Store instructions .. Double-Precision Floating-Point Computational instructions .

7 Double-Precision Floating-Point Conversion and Move instructions .. Double-Precision Floating-Point Compare instructions .. Double-Precision Floating-Point Classify Instruction .. 488 RV32/64G Instruction Set Listings499 Extending RISC-V55 Copyright 2010 2014, The Regents of the University of California. All rights Extension Terminology .. RISC-V Extension Design Philosophy .. Extensions within fixed-width 32-bit Instruction format .. Adding aligned 64-bit Instruction extensions .. Supporting VLIW encodings .. 6010 ISA Subset Naming Case Sensitivity .. Underscores .. Base Integer ISA .. Instruction Extensions Names .. Version Numbers .. Non-Standard Extension Names .. Annotations .. Supervisor- Level Instruction Subsets .. Supervisor- Level Extensions.

8 Naming Convention .. 6511 Q Standard Extension for Quad-Precision Quad-Precision Load and Store instructions .. Quad-Precision Computational instructions .. Quad-Precision Convert and Move instructions .. Quad-Precision Floating-Point Compare instructions .. Quad-Precision Floating-Point Classify Instruction .. 6912 L Standard Extension for Decimal Decimal Floating-Point Registers .. 7113 C Standard Extension for Compressed Instructions73viVolume I: RISC-V user - Level ISA B Standard Extension for Bit Manipulation7515 T Standard Extension for Transactional Memory7716 P Standard Extension for Packed-SIMD Instructions7917 RV128I Base Integer Instruction Set8118 Calling C Datatypes and Alignment .. RVG Calling Convention .. Soft-Float Calling Convention .. 8519 History and History from Revision of ISA manual .

9 Developments since Revision of ISA manual .. Acknowledgments .. Funding .. 90 Chapter 1 IntroductionRISC-V (pronounced risk-five ) is a new Instruction set architecture (ISA) that was originallydesigned to support computer architecture research and education, but which we now hope willbecome a standard open architecture for industry implementations. Our goals in defining RISC-Vinclude: A completelyopenISA that is freely available to academia and industry. ArealISA suitable for direct native hardware implementation, not just simulation or binarytranslation. An ISA that avoids over-architecting for a particular microarchitecture style ( , mi-crocoded, in-order, decoupled, out-of-order) or implementation technology ( , full-custom,ASIC, FPGA), but which allows efficient implementation in any of these. An ISA separated into asmallbase integer ISA, usable by itself as a base for customizedaccelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.

10 Support for the revised 2008 IEEE-754 floating-point standard [8]. An ISA supporting extensive user - Level ISA extensions and specialized variants. Both 32-bit and 64-bit address space variants for applications, operating system kernels, andhardware implementations. An ISA with support for highly-parallel multicore or manycore implementations, includingheterogeneous multiprocessors. Optionalvariable-length instructionsto both expand available Instruction encoding space andto support an optionaldense Instruction encodingfor improved performance, static code size,and energy efficiency. A fully virtualizable ISA to ease hypervisor development. An ISA that simplifies experiments with new supervisor- Level and hypervisor- Level ISA on our design decisions is formatted as in this paragraph, and can be skipped if thereader is only interested in the specification name RISC-V was chosen to represent the fifth major RISC ISA design from UC Berkeley(RISC-I [16], RISC-II [9], SOAR [23], and SPUR [12] were the first four).