Set-Associative Cache Architecture
Chapter 5 —Set Associative Caches 10 Cortex-A8 Data Cache Miss Rates FIGURE 5.45 Data cache miss rates for ARM Cortex-A8 when running Minnespec, a small version of SPEC2000.Applications with larger memory footprints tend to have higher miss rates in both L1 and L2. Note that the L2 rate is the global miss rate; that is, counting all references,
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