7 Series Product Tables and Product Selection Guide

1 Page 2 Spartan-7 with the same last letter and number sequence, , A484, are footprint compatible with all other Spartan-7 devices with the same sequence. The footprint compatible devices within this family are outlined. I/O Optimization at the Lowest Cost andHighest Performance-per-Watt( , )Part NumberXC7S6XC7S15XC7S25XC7S50 XC7S75XC7S100 Logic ResourcesLogic Cells6,00012,80023,36052,16076,800102,40 0 Slices9382,0003,6508,15012,00016,000 CLB Flip-Flops7,50016,00029,20065,20096,0001 28,000 Memory ResourcesMax. Distributed RAM (Kb)701503136008321,100 Block RAM/FIFO w/ ECC (36 Kb each)510457590120 Total Block RAM (Kb)1803601,6202,7003,2404,320 Clock ResourcesClock Mgmt Tiles (1 MMCM + 1 PLL)223588I/O ResourcesMax.

2 Single-Ended I/O Pins100100150250400400 Max. Differential I/O Pairs484872120192192 Embedded Hard IP ResourcesDSP Slices102080120140160 Analog Mixed Signal (AMS) / XADC001111 Configuration AES / HMAC Blocks001111 Speed GradesCommercialTemp (C)-1,-2-1,-2-1,-2-1,-2-1,-2-1,-2 Industrial Temp (I)-1,-2,-1L-1,-2,-1L-1,-2,-1L-1,-2,-1L- 1,-2,-1L-1,-2,-1 LExpanded Temp (Q)-1-1-1-1-1-1 Package(1)Body Area (mm)Ball Pitch(mm)Available User I/O: SelectIO HR 3 Artix-7 PCI Express Base specification at Gen1 and gen2 data the maximum number of transceivers available. Note that the majority of devices are available without transceivers. See the Package section of this table for package option available for all packages.

3 See DS180, 7 Series FPGAs Overviewfor package migration is available within the Artix-7 family for like packages but is not supported between other 7 Series in FGG484 and FBG484 are footprint compatible. in FGG676 and FBG676 are footprint Optimization at the Lowest Cost and Highest DSP Bandwidth ( , , )Part Number XC7A12 TXC7A15 TXC7A25 TXC7A35 TXC7A50 TXC7A75 TXC7A100 TXC7A200 TLogicResourcesLogic Cells 12,80016,64023,36033,28052,16075,520101, 440215,360 Slices2,0002,6003,6505,2008,15011,80015, 85033,650 CLB Flip-Flops 16,00020,80029,20041,60065,20094,400126, 800269,200 MemoryResourcesMaximum Distributed RAM (Kb)1712003134006008921,1882,888 Block RAM/FIFO w/ ECC (36 Kb each)2025455075105135365 Total Block RAM (Kb)7209001,6201,8002,7003,7804,86013,14 0 Clock ResourcesCMTs (1 MMCM + 1 PLL)

4 353556610I/O ResourcesMaximum Single-Ended I/O150250150250250300300500 Maximum Differential I/O Pairs7212072120120144144240 Embedded Hard IP ResourcesDSP Slices40458090120180240740 PCIe gen2 (1)11111111 Analog Mixed Signal (AMS) / XADC11111111 Configuration AES / HMAC Blocks11111111 GTP Transceivers ( Gb/s Max Rate)(2)244448816 Speed GradesCommercial Temp(C)-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2 ExtendedTemp (E)-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3 Industrial Temp (I)-1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1L-1, -2, -1 LPackage(3), (4)Dimensions (mm)Ball Pitch(mm)Available User I/O: SelectIO HR I/O (GTP Transceivers)CPG23610 x (2)106 (2)106 (2)CPG23810 x (2)112 (2)CSG32415 x (0)210 (0)210 (0)210 (0)210 (0)CSG32515 x (2)150 (4)150 (4)150 (4)150 (4)FTG25617 x (0)170 (0)170 (0)170 (0)170 (0)SBG48419 x (4)FootprintCompatibleFGG484(5)23 x (4)250 (4)250 (4)285 (4)285 (4)FBG484(5)23 x (4)FootprintCompatibleFGG676(6)27 x (8)300 (8)FBG676(6)27 x (8)FFG115635 x (16)Page 4 Kintex-7 solutions provide a fast and conversion-free path for cost block supports PCI Express Base specification at Gen1 and gen2 data rates.

5 Gen3 supported with soft DS180, 7 Series FPGAs Overview,for package transceivers in FB packages support the following maximum data rates: in FBG484; in FBG676 and FBG900. See DS182, Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics, for for Best Price-Performance( , , )Part Number XC7K70 TXC7K160 TXC7K325 TXC7K355 TXC7K410 TXC7K420 TXC7K480 TEasyPath Cost Reduction solutions (1) XCE7K325 TXCE7K355 TXCE7K410 TXCE7K420 TXCE7K480 TLogic ResourcesSlices10,25025,35050,95055,6506 3,55065,15074,650 Logic Cells65,600162,240326,080356,160406,7204 16,960477,760 CLB Flip-Flops 82,000202,800407,600445,200508,400521,20 0597,200 MemoryResourcesMaximum Distributed RAM (Kb) 8382,1884,0005,0885,6635,9386,788 Block RAM/FIFO w/ ECC (36 Kb each) 135325445715795835955 Total Block RAM (Kb)4,86011,70016,02025,74028,62030,0603 4,380 Clock ResourcesCMTs (1 MMCM + 1 PLL)

6 681061088I/O ResourcesMaximum Single-Ended I/O300400500300500400400 Maximum Differential I/O Pairs144192240144240192192 Integrated IP ResourcesDSP48 Slices2406008401,4401,5401,6801,920 PCIe gen2 (2)1111111 Analog Mixed Signal (AMS) / XADC1111111 Configuration AES / HMAC Blocks1111111 GTX Transceivers ( Gb/s Max Rate)881624163232 Speed GradesCommercial Temp(C)-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2 ExtendedTemp (E)-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3 Industrial Temp (I)-1, -2-1, -2, -2L-1, -2, -2L-1, -2, -2L-1, -2, -2L-1, -2, -2L-1, -2, -2 LPackage(3)Dimensions (mm)BallPitch(mm)Available User I/O: HR I/O, HP I/Os (GTX)FBG484(4)23 x , 100 (4)185, 100 (4)FootprintCompatibleFBG676(4)27 x , 100 (8)250, 150 (8)250, 150 (8)250, 150 (8)FFG67627 x , 150 (8)250, 150 (8)250, 150 (8)FootprintCompatibleFBG900(4)31 x , 150 (16)350, 150 (16)FFG90031 x , 150 (16)350, 150 (16)FFG90131 x , 0 (24)380, 0 (28)380, 0 (28)FFG115635 x , 0 (32)400, 0 (32)Virtex-7 FPGAsOptimized for Highest System Performance and Capacity( )Part Number XC7V585 TXC7V2000 TXC7VX330 TXC7VX415 TXC7VX485 TXC7VX550 TXC7VX690 TXC7VX980 TXC7VX1140 TXC7VH580 TXC7VH870 TEasyPath Cost Reduction solutions (1)

7 XCE7V585T XCE7VX330 TXCE7VX415 TXCE7VX485 TXCE7VX550 TXCE7VX690 TXCE7VX980T Logic ResourcesSlices91,050305,40051,00064,400 75,90086,600108,300153,000178,00090,7001 36,900 Logic Cells582,7201,954,560326,400412,160485,7 60554,240693,120979,2001,139,200580,4808 76,160 CLB Flip-Flops 728,4002,443,200408,000515,200607,200692 ,800866,4001,224,0001,424,000725,6001,09 5,200 MemoryResourcesMaximum Distributed RAM (Kb) 6,93821,5504,3886,5258,1758,72510,88813, 83817,7008,85013,275 Block RAM/FIFO w/ ECC (36 Kb each) 795 1,292 750 8801,0301,1801,4701,5001,8809401,410 Total Block RAM (Kb) 28,62046,51227,00031,68037,08042,48052,9 2054,00067,68033,84050,760 ClockingCMTs (1 MMCM + 1 PLL) 1824141214202018241218I/O ResourcesMaximum Single-Ended I/O8501,2007006007006001,000 9001,100600300 Maximum Differential I/O Pairs408576336288336288480432528288144 Integrated IP ResourcesDSP Slices 1,260 2,160 1,120 2,160 2,800 2,880 3,600 3,600 3,360 1,680 2,520 PCIe gen2 (2)3 4 4 PCIe Gen3 22 233423 Analog Mixed Signal (AMS) / XADC11111111111 Configuration AES / HMAC Blocks11111111111 GTX Transceivers ( Gb/s Max Rate)(3)3636 56 GTH Transceivers ( Gb/s Max Rate)(4) 2848 808072964872 GTZ Transceivers ( Gb/s Max Rate) 816 Speed GradesCommercial Temp(C)-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2 ExtendedTemp (E)(5)

8 -2L, -3-2L, -2G-2L, -3-2L, -3-2L, -3-2L, -3-2L, -3-2L-2L, -2G-2L, -2G-2L, -2 GIndustrial Temp (I)-1, -2-1-1, -2-1, -2-1, -2-1, -2-1, -2-1-1 Package(6)Dimensions (mm)Ball Pitch(mm)Available User I/ HR I/O, HP I/Os (GTX, GTH) HP I/O (GTH, GTZ)FFG1157(7)35 x , 600 (20, 0)0, 600 (0, 20)0, 600 (0, 20)0, 600 (20, 0)0, 600 (0, 20)Footprint CompatibleFFG1761(7) x , 750 (36, 0)50, 650 (0, 28)0, 700 (28, 0)0, 850 (0, 36)FHG176145 x , 850 (36, 0)FLG192545 x , 1200 (16, 0)FFG1158(7)35 x , 350 (0, 48)0, 350 (48, 0)0, 350 (0, 48)0, 350 (0, 48)Footprint CompatibleFFG192645 x , 720 (0, 64)0, 720 (0, 64)FLG192645 x , 720 (0, 64)FFG1927(7)45 x , 600 (0, 48)0, 600 (56, 0)0, 600 (0, 80)0, 600 (0, 80)Footprint CompatibleFFG192845 x , 480 (0, 72)FLG192845 x , 480 (0, 96)Footprint CompatibleFFG193045 x , 700 (24, 0)0, 1000 (0, 24)0, 900 (0, 24)FLG193045 x , 1100 (0, 24)FLG115535 x (24, 8)FLG193145 x (48, 8)FLG193245 x (72, 16) solutions provide a fast and conversion-free path for cost block supports PCI Express Base specification at Gen1 and gen2 data rates.

9 Gen3 supported with soft Gb/s support in "-3E", "-2GE" speed/temperature grade; Gb/s support in "2C", "-2LE", and "-2I" speed Gb/s support in "-3E". "-2GE" speed grade; Gb/s support in "2C" , "-2LE" and "-2I" speed/temperature only applies to Stacked Silicon Interconnect devices and supports GTX, GTH, GTZ with -2 package options ("FFxxxx"/"FLxxxx"/"FHxxxx") available for all packages. "HCxxxx" is not offered in a leaded DS180, 7 Series FPGAs Overviewfor package 6 Device Ordering InformationNotes:-L1 is the ordering code for the lower power, -1L speed is the ordering code for the lower power, -2L speed = Commercial (Tj = 0 C to +85 C) E = Extended (Tj = 0 C to +100 C) I = Industrial (Tj = 40 C to +100 C) Q = Expanded (Tj= 40 C to +125 C)Xilinx CommercialGenerationXC7 KFamily###Logic Cellsin 1K Units-1 Speed Grade-1 = Slowest-L2 = Low Power-2 = Mid -3 = HighestFFPackage TypeFB: Bare-Die Flip-Chip (1 mm)FF.

10 Flip-Chip (1 mm)900 Nominal Package Pin CountCTemperature Grade(C, E, I)Xilinx CommercialGenerationXC7 VFamilyLogic Cellsin 1K Units-1 Speed Grade-1 = Slowest-2 = Mid -L2 = Low Power-3 = HighestFF1156 NominalPackage Pin CountCTemperature Grade(C, E, I)Package TypeFF: Flip-Chip (1 mm)FH: Flip-Chip (1 mm)FL: Flip-Chip (1 mm)HC: Ceramic Flip-Chip (1 mm)###Xilinx CommercialGenerationXC7 AFamily###Logic Cellsin 1K Units-1 Speed Grade-1 = Slowest-L1 = Low Power-L2 = Low Power-2 = Mid -3 = HighestFBPackage TypeCP: Wire-bond (.5 mm)CS: Wire-bond (.8 mm)FB: Bare-Die Flip-Chip (1 mm) FF: Flip-Chip (1 mm) FG: Wire-bond (1 mm)FT: Wire-bond (1 mm)SB: Bare-DieFlip-Chip (.8 mm)484 NominalPackage Pin CountCTemperature Grade(C, E, I)GV: RoHS 6/6G: RoHS 6/6 w/Exemption 15GV: RoHS 6/6G: RoHS 6/6 w/Exemption 15GV: RoHS 6/6G: RoHS 6/6 w/Exemption 15 CommercialXilinx GenerationXC7###Logic CellsIn 1K units-1 Speed Grade-1 = Slowest-L1 = Low Power-2 = Mid FGPackage TypeCP: Wire-bond (.)