VHDL04 chapter1.ppt [호환 모드] - dasan.sejong.ac.kr

1 vhdl vhdl 4. vhdl process if , case vhdl code 2/47 ContentContent (Sequential Statements)if if case loop (Concurrent Statements) (Concurrent Statements) process conditional signal assignment selected signal assignment selected signal assignment 3/47 Concurrent StatementsConcurrent Statements architecture body concurrent statement concurrent statement architecture test1 of test isbeginA<=BorC;architecture test2 of test isbeginC<=notE;A <= B or C;B <= D and E;C <= not E;C <= not E;B <= D and E;A <= B or C;=end test1;end test2;concurrent statement 4/47concurrent statement Concurrent StatementsConcurrent Statements process (process statement) process (process statement) concurrent signal assignment tti concurrent assertion concurrent procedure call p component instantiation generate ( ) generate ( )5/47 Concurrent StatementsConcurrent Statements process concurrent statement statement process sequential p qstatement dlt ti l delta : process sequential statement concurrent signal assignment statement process statement process 6/47 Concurrent Statements(b )Concurrent Statementsprocess (b, c) beginABCA <= B or C;end process;A <= B or C;B < D and E.

2 Process (b, c) beginXtbB <= D and E;C <= not E;X <= not b;end process;=process (b, c) beginbb <= c xor y;end process;7/47concurrent statement Concurrent StatementsConcurrent Statements process statementiii li i sensitivity list wait . process concurrent , process sequential pq process declaration part signal declaration variabledeclaration , variable declaration 8/47 Concurrent StatementsConcurrent Statements Syntax :[label:] process[ (sensitivity_list) ][variable_decl][constant_decl][type_decl][subprogram_body][][use_clause][alias_decl][fil d l][file_decl]begin <tilttt> <sequential statements>end process[label] ;9/47 Concurrent StatementsConcurrent Statements concurrent signal assignment statement( )statement( ) signal assignment process , process simple signal assignment conditional signal assignment selected signal assignment selected signal assignment 10/47 Concurrent StatementsConcurrent Statements simple signal assignment statement Syntax Syntax [lable:] signal_name <= expression [after time expr];time_expr]; ) qa <= r or t after 1 ns;(())qb <= (qaand not(g xor h)) after 2 ns.

3 11/47 Concurrent StatementsConcurrent Statements selected signal assignment statement multiplexer Syntax : case [label:] with expression selectsignal_name <= expression when value{ , expression when value}{ , expression when others} ) with MYSEL selectZ <= A when 15, B when 22,C when 28 D when others;12/47C when 28, D when others;Concurrent StatementsConcurrent Statements conditional signal assignment statement signal signal priority encoder St :ifl Syntax : if-else [label:] signal_name <= expression when condition else{expression when condition else}expression; ) :Z <= A when (X > 3) elseB when (X < 3) elseC; -- X = 313/47 Concurrent StatementsConcurrent Statements 14/47 Delay Model( )Delay Model( ) delta delay model( ) delta delay model( ) inertial delay model( )ttdl dl( ) transport delay model( )15/47 Delay Model( )Delay Model( ) 0 ns 16/47 Delay Model( )Delay Model( ) ABCYB <= not A; C <= not B; Y <= not C.

4 ABCYAABCYY10 ns10+1 10+2 10+3 =10 ns17/47 Delay Model( )Delay Model( ) default delay model18/47 Delay Model( )Delay Model( ) Syntax Syntax signal_name <= [[rejectpulse_rejection_limit] inertial]expressionafterinertial delay value;expression afterinertial_delay_value; ) :Y <= reject4 ns A after10 ns;delay = 10 nsreject limit = 4 nsAY5 8 1025 28 3045 48reject limit = 4 nsA5 8 10 25 28 30 45 48Y19/4720 40 Delay Model( )Delay Model( ) Y<=inertial A after 10 ns; Y < inertial A after 10 ns; -- same as Y <= A after 10 ns --same as Y <= reject 10 ns inertial A after 10 ns; same as Y <= reject 10 ns inertial A after 10 ns;X < reject 4 ns inertial A after 10 ns; X <= reject 4 ns inertial A after 10 ns; -- same as X <= reject 4 ns A after 10 ns delay default 20/47 Delay Model( )Delay Model( ) transport 21/47 Delay Model( )Delay Model( ) Syntax Syntax signal_name <= transport expression after transport delay value;transport_delay_value; ) :Y <= transportA after10 ns.

5 Delay = 10 nsAY5 8 1025 28 3045 48A5 8 10 25 28 30 45 48Y22/4715 18 20 35 38 40 55 58 Concurrent StatementsConcurrent Statements concurrent procedure calldllttt procedure call statement process procedure : in, inout, outSyntax Syntax <procedure_name> ()(<actual_parameter_list>);23/47 Concurrent StatementsConcurrent Statements Example :architecture .. isprocedure VEC2 INT(signal s : in bit_vector;signal ZFLAG : outboolean;signal ZFLAG : out boolean;signal Q : inout integer;) VEC2 INT;..beginbeginVEC2 INT (BITVEC, FLAG, NUMBER);..end arch;24/47 Concurrent StatementsConcurrent Statements block statementttt t concurrent statement . block block block declaration part type, constant signal subprogram constant, signal, subprogram block scope 25/47 Concurrent StatementsConcurrent StatementsSyntax Syntaxlabel : block [(guard_expression)][port clause;port map clause][port_clause; port_map_clause][use_clause][subprogram declsubprogram body][subprogram_declsubprogram_body][ty pe_decl][subtype decl][subtype_decl][constant_decl][signa l decl][signal_decl][conponent_decl]beging [concurrent_statements]end block [label];26/47 Concurrent StatementsConcurrent StatementsEl: Example :architecture arck_blk of BLOCKSTMT : SHIFT port map (rst=>rst, clk=>clk, si=>t1, so=>t1).

6 Block0 : blockbeginbeginstate1 : SHIFT port map(rst=>rst, clk=>clk, si=>t1, so=>t2);state0 : SHIFT port mapstate0 : SHIFT port map(rst=>rst, clk=>clk, si=>t2, so=>so);end block;end arch_blk;_stage2block0clkrstsogsi27/47 Concurrent StatementsConcurrent Statementsbl k bl k h d t block block_head port map bloc block header : block_header :entityBKHEAD isport(DA,DB : instd_logic; DZ : outstd_logic);end BKHEAD;architectureBEH ofBKHEWAD isbeginbeginblock0 : blockport(A,B : instd_logic; z : outstd_logic);port map(A=>DA, B=>DB, Z=>DZ);beginZ<=AnandB;Z <= A nandB;end block;endBEH;28/47 Concurrent StatementsConcurrent Statements concurrent assertion statement sequential assertion statement assert process condition false condition false Syntax :[label:]assert<condition>[label:] assert<condition>[report<string_type expression>] [severityNOTE|WARNING|ERROR|FATAL] ;[severityNOTE|WARNING|ERROR|FATAL] ;29/47 Concurrent StatementsConcurrent Statements Example ;entityASSRT endASSRT ;architectureBEH ofASSRT issignalS, Y ; std_logic;g, : assertY = S report not equal severity NOTE;asrt1: assertFALSE report start to compare severityNOTE;endBEH.

7 30/47 Concurrent StatementsConcurrent Statements Severity note : note warning : warning , error: error , , warning error fatal : fatal , 31/47 Concurrent StatementsConcurrent Statements component instantiation statement Syntex :ylabel : component_name[generic map( <generic_mapping> )][port map(<signal mapping>)];[port map( <signal_mapping> )] ; Example: Example: H0 : HA port map(A=>X, B=>Y, Sum=>t_s, Carry=>t_c1); u_or : OR2 generic map (delay => 1 ns) port map (i1=>t_c1, i2=>t_c2, z=>Cout);32/47 Concurrent StatementsConcurrent Statementsgenerate statement( ) generate statement( ) , , Simulation Simulation For-Generate : elaboration If-Generate : 33/47 Concurrent StatementsConcurrent Statements generate statement( ) Syntex : For-Generate tlblfiblitgenerate_label: forvariableinrangegenerate[<block_declarative_item>begin]begin ]<concurrent_statement>end generate[generate_label]; Syntex : If-Generate generate label:ifconditiongenerategenerate_label ifconditiongenerate[<block_declarative_item>begin ]<ttt t> <concurrent_statement>end generate[generate_label].

8 34/47 Concurrent StatementsConcurrent Statements Example :beginU0: FullAdder1 port map(X=>DA(0), Y=>DB(0), Cin=>Ci, Cout=>t(0), ())begingen0 : foriin0 to 3 generateSout=>S(0));U1: FullAdder1 port map(X=>DA(1), Y=>DB(1), Cin=>t(1), Cout=>t(1), Sout=>S(1));U0: FullAdder1 port map(X=>DA(i), Y=>DB(i), Cin=>t(i), Cout=>t(i+1), Sout=>S(i));Sout>S(1));U2: FullAdder1 port map(X=>DA(2), Y=>DB(2), Cin=>t(2), Cout=>t(2),Sout=>S(2));U3 F llAdd 1(X DA(3)Sout>S(i));end generate;t(0) <= Ci; =U3: FullAdder1 port map(X=>DA(3), Y=>DB(3), Cin=>t(2), Cout=>Co, Sout=>S(3));endstruct top;Co <= t(4);endstruct_gen ;endstruct_top;35/47 Sequential StatementsSequential Statements process subprogram Process Process Process Process 36/47 Sequential StatementsSequential Statements signal assignment gg variable assignment if case if , case wait assert assert loop ill exit, next, null return procedure call or function call37/47 Sequential StatementsSequential Statements wait Process suspend Syntex :wait [on <signal_list> [until] <condition>] [for <time>].

9 Ibl i t variable assignment Syntax :<variable name> := <expression> signal assignment Syntax :<signal name> <= [transport|inertia] <expression> after<time delay>];<time delay>]; process 38/47 process Sequential StatementstSequential Statements assert process assert assert Syntax : Syntax :[label:] assert<condition> [report<string_type expression>] [severityNOTE|WARNING|ERROR|FATAL];[seve rityNO