Chapter 16.1 NMOS Inverter - Introduction to VLSI

1 1 Chapter 16 NMOS InverterChapter In the late 70s as the era of LSI and VLSI began, NMOS became the fabrication technology of choice. Later the design flexibility and other advantages of the CMOS were realized, CMOS technology then replaced NMOS at all level of integration. The small transistor size and low power dissipationof CMOS circuits, demonstration principal advantages of CMOS over NMOS Digital CircuitsNMOS Inverter For any ic technology used in digital circuit design, the basic circuit element is the logic Inverter . Once the operation and characterization of an Inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits. MOSFET Digital Circuits2n-channel MOSFETn-channel MOSFETn-Channel MOSFET Formulas Transition points Saturation region Nonsaturation region Inverter For any ic technology used in digital circuit design, the basic circuit element is the logic Inverter . Once the operation and characterization of an Inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits.

2 3++VGS=NMOS Inverter As the input voltageincreases(VGS), the drain to source voltage (VDS) decreases and the transistor inter into the nonsaturation region. IfVI <VTN, the transistor is in cutoffand iD= 0, there is no voltage drop across RD, and the output voltage is Vo=VDD=VDS=VDD=VDSVI <VNTT ransistor offVI >VNTT ransistor on If VI >VTN, the transistor is onand initially is biased in saturation region, since VDS< VGS-VTN.++VGS==VDD=VDSCut-offNMOS Inverter with Resister Load IfVI <VTN, the transistor is in cutoffand iD= 0, there is no voltage drop across RD, and the output voltage is Vo=VDD=VDS As the inputis increased slightly above the VTN, the transistor turns onand is in the saturation region. ++VGS==VDSS aturation RegionNMOS Inverter with Resister LoadSaturation regionTransition RegionNMOS Inverter with Resister Load The Q-point of the transistor moves up the load line. As theinputvoltage is further increases and voltage drop across the RDbecome sufficient to reduce the VDSsuch that TNGSDSVVV ++VGS==VDSAt the transition point,Saturation region4 As theinputvoltage becomes greater than VIt, the Q-point continues to move up the load line, and the transistor becomes biased in the nonsaturation RegionSaturation region++VGS==VDSN onsaturation regionNMOS Inverter with Resister LoadVGS= vIVDS= vONMOS Inverter with Resister Load++VGS==VDST hesharpnessof the transition region increases with increasing load minimum output voltage, or the logic 0level, for a high input decreaseswith increasing load RelationshipSummary of NMOS Inverter with Resister LoadCurrent-Voltage RelationshipNonsaturation RegionSaturation RegionTransition Region ExampleFor the NMOS Inverter shown in Fig.

3 VDD= 3V. Assume transistor parameters of K n= 60 A/v2, W/L = 5, and VTN= V. (a) Find the value of RDsuch that vo= V when vI= 3 V. (b) Using the results of part (a) determine the transition point for the driver transistor5n-Channel MOSFET connected as saturated load device An n-channel enhancement-mode MOSFET with the gate connected to the drain can be used as load device in an NMOS Inverter . Since the gate and drain of the transistor are connected, we haveVGS=VDSWhen VGS=VDS>VTN, a non zero drain current is induced in the transistor and thus the transistor operates in saturation only. And following condition is >(VGS-VTN) VDS(sat)= (VDS-VTN) because VGS=VDS or VDS(sat)= (VGS-VTN)In the saturation region the drain current is iD=Kn(VGS-VTN)2= Kn(VDS-VTN)2 The iDversus vDScharacteristics are shown in Figure (b), which indicates that this device acts as a nonlinear Inverter with Enhancement Load This basic Inverter consist of two enhancement-only NMOS transistors Much more practical than the resisterloaded Inverter , because theresistors are thousand of times largersize than a Inverter withEnhancement Load An n-channelenhancement-mode MOSFET withgate connected to the draincan be used as a load acts as a Nonlinear resistor!

4 !!Nonlinear resistor!!!6 NMOS Inverter with Enhancement LoadWhen vI< VTNDNMOS Inverter with Enhancement LoadWhen vI> VTNDJust greater thanNMOS Inverter with Enhancement LoadNMOS Inverter with Enhancement LoadWhen vI> VIt7 NMOS Inverter with Enhancement LoadNMOS Inverter with Resister Load++VGS==VDST hesharpnessof the transition region increases with increasing load minimum output voltage, or the logic 0level, for a high input decreaseswith increasing load Inverter with Enhancement LoadLimitation of Enhancement Load inverterExampleP10148 Limitation of Enhancement Load inverterExample enhancement-load NMOS Inverter shown in Fig. is biased at VDD= 3 V. The transistor parameters are VTND= VTNL= V, k n= 60 mA/V2, (W/L)D= 16 and (W/L)L= 2. (a) Find vowhen (i) vI= 0, (ii) vI= , (b) Calculate the power dissipated in the Inverter when vI= V. 9 NMOS Inverter with Depletion Load This is an alternate form of the NMOS Inverter that uses an depletion-mode MOSFET load device with gate and source terminal connected.

5 This Inverter has the advantage of VO= VDD, as well as more abrupttransition region even though the W/Lratiofor the output MOSFET is mode: Channel existseven with zero gate negativevoltagemust be applied to the gate to turn thedevice voltageis Depletion-Mode MOSFET In n- channel depletion mode MOSFET, an n-channel region or inversion layer exists under the gate oxide layer even at zero gate voltage and hence term depletion mode. A negative voltage must be applied to the gate to turn thedevice off. Thethreshold voltageis alwaysnegativefor this kind of Inverter with Depletion LoadGate and source are connected,Since the threshold voltageof load transistor is Inverter with Depletion Load10 NMOS Inverter with Depletion Load (cont.)Case I:when VI<VTND(drive is cutoff): No drain current conduct in either transistor. That means the load transistor must be in the linear region of the operation and the output current can be expressed as fellowsiDL(linear)=KL[2(VGSL-VTNL)VDSL-VDSL2]Since VGSL=0, and iDL=00=-KL[2 VTNLVDSL+ VDSL2]Which gives VDSL=0 thusVO= VDDThis is the advantage of the depletion load Inverter over the enhancement load > VTNDJust greater thanNMOS Inverter with Depletion LoadNMOS Inverter with Depletion LoadThis implies that input voltageis constant as theQ-point passes this Inverter with Depletion LoadThis implies that input and output voltages are not linearin this Inverter with Depletion LoadQ1Q2(Nonsaturation)

6 More abrupttransition region can be achieved even though the W/Lratiofor the output MOSFET is Inverter with Depletion LoadExample next slidevGS=0 See slide 3412 Example next slidevGS=0 Summary of NMOS Inverter with Resister LoadCurrent-Voltage RelationshipNonsaturation RegionSaturation RegionTransition RegionExample transistor is in Saturation mode Design (i)(ii)Example (i)(ii)Example (i)(ii)1160 W825 W200 WExample LoadResister LoadEnhancement LoadNMOS InverterChapter 16 NMOS Logic CircuitChapter logic circuitsare constructed by connecting driver transistor in parallel, series orseries-parallel combinationsto produce required output logic functionNMOS Logic CircuitLogic GatesIn 01 OutAND GateOR GateIn 01 OutXOR GateIn 01 OutInOutNOT GateLogic GatesNMOS NORGate NMOS NOR gate can be constructed by connecting an additional driver transistorin parallelwith a depletion load NORGateNMOS NORGateWhen all Inputs are at logic 1 When A = B = logic 1 Both driver transistorsare switched into nonsaturation regionand load transistor is biased in saturation two driver transistors are identical.

7 Higher the aspect ratio lower the NANDGateAdditional driver transistor connected in Series17 For the NOR gatethe effective width of the drivers transistors effective aspect ratio is the NAND gatethe effective length of the driver transistors effective aspect ratio is combinationSeries combinationNMOS Logic CircuitConcept of Effective Width-to-Length RatiosDesign (a)Design (b)(c)18 The Fan-inof a gate is the number of its inputs. Thus a four input NOR gate has a fan-in of 4. Similarly, Fan-Outis the maximum number of similar gates that a gate can drive while remaining within guaranteed and Fan-OutThe rate at Transient Analysis of NMOS Inverters The constant current over a wide range of VDSprovided by the depletion load implies that this type of Inverter switch a capacitive load more rapidly than the other two types Inverter configurations. The source of capacitanceCT2andCT3are the transistor input capacitancesand parasitic capacitancesdue to interconnect lines between the Inverter stages.

8 The raise timeis longer because the load capacitor is charged by the current through the smaller load transistor. The fall timerelatively short, because the load capacitor discharges through the large driver transistor.(W/L)L=1(W/L)D= Analysis of NMOS Inverters Chapter 16 CMOS InverterChapter MOSFET ppnpn In p-channel enhancement device. A negative gate-to-source voltage must be applied to create the inversion layer, or channel region, of holes that, connect the source and drain regions. The threshold voltageVTPfor p-channel enhancement-modedevice is always negativeandpositivefor MOSFETC ross-section of p-channel enhancement mode MOSFETC omplementary MOSCMOSThe most abundant devices on earth Although the processing is more complicated for CMOS circuits than for NMOS circuits, CMOS has replaced NMOSat all level of integration, in both analog and digital applications. The basic reason of this replacement is that the power dissipation in CMOS logic circuitsis much less than in NMOS Properties Full rail-to-rail swing high noise marginszLogic levels not dependent upon the relative device sizes transistors can be minimum size ratio less Always a path to VDDor GND in steady state low output impedance(output resistance in k range) large fan-out.

9 Extremely high input resistance(gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay functionof load capacitance and resistance of transistors In the fabrication process, a separate p-wellregion is formed within the starting n-substrate. The n-channel MOSFET is fabricated in the p-well region and p-channel MOSFET is fabricated in the InverterSteady State ResponseVDDRnVOut= 0 VIn= VDDVDDRpVOut= VDDVIn= 0 CMOS InverterDDOHOLVVV==0 PMOSNMOSPMOSNMOS21 Voltage Transfer Curve22HW Inverter Load (A)Vout(V)X10-4 Vin= , W/Ln= , W/Lp= , VDD= , VTn= , VTp= 0 VVin= (A)NMOS offPMOS in non satNMOS in satPMOS in non satNMOS in satPMOS in satNMOS in non satPMOS in satNMOS in nonsatPMOS off24vSDPis smallvIand vOrelationship as long as NMOS: saturation, PMOS: nonsaturationfrom below graphvOPtorfrom above graphvONtvItBC25 NMOS: nonsaturationPMOS: offNMOS: nonsaturationPMOS: saturationNMOS: saturationPMOS: saturationNMOS: saturationPMOS: nonsaturationNMOS: offPMOS: nonsaturationExample VDD=5 VExample The transistor KNis also known as pull down device because it is pulling the output voltage down towards ground.

10 The transistor KPis known as the pull up device because it is pulling the output voltage up towards VDD. This property speed up the operation static power dissipationduring both extreme cases (logic 1 or 0) is almost zerobecause iDP= iDN= CMOS Inverter : series combination of PMOS and NMOS To form theinput, gates of the two MOSFET are connected. To form the output, the drains are connected together.(ideal case)Ideally, the power dissipation of the CMOS Inverter is deviceCMOS Inverter ( nW) NMOS Inverter ( mW)CMOS Inverter in either High or Low StateCMOS Inverter Design Consideration The CMOS Inverter usually design to have, 9 This can achieved if width of the PMOSis made two or three times than that of the NMOS device. 9 This is very important in order to provide a symmetrical transition, results in wide noise (because N> P)(1)(2)TPTNVV= = LWkLWkPN''''PNkk> How equation (2) can be satisfied ?27 NMOS: nonsaturationPMOS: offNMOS: nonsaturationPMOS: saturationNMOS: saturationPMOS: saturationNMOS: saturationPMOS: nonsaturationNMOS: offPMOS: nonsaturationSymmetricalProperties of the CMOS InvertervOPtvONt2 DDItVV=p1101vItvOPtvONt =LWkKnN2'(a)(i)Transition pointsVOPtVONt(ii)28 Example (b)(i)(ii)Transition pointsVOPtVONt =LWkKPP2'Increase Wof PMOS kPincreases VItmoves to rightVDDVDDVInVOutkp=5knkp=knkp= Inverter VTCI ncrease Wof NMOS kNincreases VItmoves to leftPNPNDDItWWkkVVfor = =,2 VIt Result from changing kP/kNratio: Inverter threshold VIt VDD/2 Rise and fall delays unequal Noise margins not equal Reasons for changing Inverter threshold: Want a faster delayfor one type of transition (rise/fall) Removenoisefrom input signal.