EE 435 - Iowa State University

1 ee 435 Lecture 24 Data ConvertersBasic Operation of CMFB BlockVDDM1M2VB2M3M4 VINVINCLM9 CLVOUTVOUTCMFBC ircuitVOXXVFBCMFBC ircuitVOXXVFBVO1VO2 VOXXVFBVO1VO2 AveragerAVAVGCMFB Block 0102 FBV +VV =A s2 VOXXis the desired quiescent voltage at the stabilization node (irrespective of where VFBgoes). Review from last lecture . Common-mode offset voltageM1M2VC1M3M4M5VO2VO1VB1 VDDVYYC1C2VC1 VCOFFV0 XXV0 XXDefinition: The common-mode offset voltage is the voltage that must be applied to the biasing node at the CMFB point to obtain the desired operating point at the stabilization node. Review from last lecture . Common-mode gainsM1M2VC1M3M4M5VO2VO1VB1 VDDVYYC1C2VC1 VCOFFV0 XXV0 XXM2VC1M4VO2VC2 CVDDM 3VC3020103 COMC105Vg +g /2A-VsC+g 02m5 COM2C205 VgA-VsC+g 02m3 COM3C305Vg /2A-VsC+g 1/ 2 20103 COM005g +g /2A-gTTII 552/4/2m5 COM2005gA-gTEBTEBIVIV Tm3EB3 COM3005 TEB32I/2g /2V2A= -gI /2V Although the common-mode gain ACOM0is very small, AC0M20is very large!

2 Shift in V02 Qfrom VOXXis the product of the common-mode offset voltage and ACOM20. Review from last lecture . How much gain is needed in the CMFB amplifier?VDDM1M2VB2M3M4 VINVINCLM9 CLVOUTVOUTCMFBC ircuitVOXXVFBThe CMFB LoopM2M 3M4VO2VC1 VDDVC3C2VC1 VCOFFVOXXVFBAVAVGCOM20UT-ACCEPTABLECOFFC OM2AV=V1-AA This does not require a particularly large gain This is the loop that must be compensated since A and ACOMP2will be frequency dependent Miller compensation capacitor for compensation of differential loop will often appear in shunt with C2 Can create this loop without CM inputs on fully differential structure for simulations Results extend readily to two-stage structures with no big surprises. Review from last lecture . CMFB CircuitsVDDIBIBVOXXVSSVSSM1M2M3M4M5M6 VFB01V02VM7 Several (but not too many) CMFB circuits existCan be classified as either continuous-time or discrete-timeC1 CSC1 CSVFB-oV+oVV01V02N1N1N1N1N2N2N2N2.

3 Review from last lecture . Data Converters Types:A/D (Analog to Digital)Converts Analog Input to a Digital Output D/A (Digital to Analog)Converts a Digital Input to an Analog OutputA/D is the world s most widely used mixed-signal componentD/A is often included in a FB path of an A/DA/D and D/A fields will remain hot indefinitelytechnology advances make data converter design more challengingembedded applicationsdesigns often very application dependentD/A ConvertersnINXDACXOUTXREFnINXDACX+OUTX+R EFX-REFX-OUTB asic structure:Basic structure with differential outputs::D/A ConvertersnINXDACXOUTXREFN otation:nXOUTDACINXnXOUTDACXREFINXD/A ConvertersINn-1 n-11 0X =<b ,b ,..b ,b >nXOUTDACINXb0is the Least Significant Bit (LSB)bn-1is the Most Significant Bit (MSB)Note: some authors use different index notationAn Ideal DAC is characterized at low frequencies by its static performanceD/A ConvertersINn-1 n-11 0X =<b ,b.

4 B ,b >nXOUTDACINXAnIdeal DAC transfer characteristic (3-bits)Code Ckis used to represent the decimal equivalent of the binary number < b0)>XOUT<0 0 0> <0 0 1> <0 1 0> <0 11> <1 0 0> <1 010> <1 1 0> <1 1 1>INXC0C1C2C3C4C5C6C7X-REFD/A ConvertersINn-1 n-11 0X =<b ,b ,..b ,b >nXOUTDACINXAnIdeal DAC transfer characteristic (3-bits)XOUTINX78 REFXC0C1C2C3C4C5C6C7 XREFD/A ConvertersINn-1 n-11 0X =<b ,b ,..b ,b >nXOUTDACINXAnIdeal DAC transfer characteristic (3-bits)All points of this ideal DAC lie on a straight lineXOUTINXC0C1C2C3C4C5C6C7X-REFD/A ConvertersnXOUTDACINX Most D/A ideally have a linear relationship between binary input and analog output Output represents a discrete set of continuous variables Typically this number is an integral power of 2, 2n is always dimensionless XOUT could have many different dimensions An ideal nonlinear characteristic is also possible (waveform generation and companding) Will assume a linear transfer characteristic is desired unless specifically stated to the contraryINXXOUTINXC0C1C2C3C4C5C6C7D/A ConvertersnXOUTDACINXn-30n-1n-21 OUTREFn-1nbbbbb=X+++.

5 ++24822 XFor this ideal DACnn-j OUTREFjj=1b=X2 X Number of outputs gets very large for n large Spacing between outputs is XREF/2nand gets very small for n largeXOUTINXC0C1C2C3C4C5C6C7D/A ConvertersnXOUTDACINX Ideal steps all equal and termed the LSB XLSB gets very small for small XREFand large If XREF=1V and n=16, then N=216 =65,536, XLSB= VXOUTINX REF LSBn2 XXC0C1C2C3C4C5C6C7 XREFD/A ConvertersnXOUTDACINXAn alternate ideal 3-bit DACI rrespective of which form is considered, the increment in the output for one Boolean bit change in the input is XLSB and the total range is 1 LSB less than XREFXOUTINXC0C1C2C3C4C5C6C7 Applications of DACs Waveform Generation Voltage Generation Analog Trim or Calibration Industrial Control Systems Feedback Element in ADCs.

6 Waveform Generation with DACsCLKG eneratorn-bit Binary CounterD/AAXOUTP eriodnExample: For n=3 XREFXREFXOUTtExample: For large nXREFXOUTtRamp (Saw-tooth) GeneratorWaveform Generation with DACsCLKG eneratorn-bit Binary CounterD/AAXOUTP eriodmExample: For n=3 XREFXREFXOUTtSine Wave GeneratornROM or RAMD istortion of the desired waveforms occurs due to both time and amplitude quantizationOften a filter precedes or follows the buffer amplifier to smooth the output waveformA/D ConvertersBasic structure:Basic structure with differential inputs/references:nOUTXADCXINXREFADCX+RE FX-REFnOUTXXINX+INX-INADCX+REFX-REFnOUTX I nput range is XREFI nput range is X+REF -X-REFI nput range is 2(X+REF -X-REF)A/D ConvertersNotation:nOUTXADCXINXREFXINADC nXOUTXINADCnXOUTXREFA/D ConvertersOUTn-1 n-2 0X=<d ,d.

7 D >d0is the Least Significant Bit (LSB)dn-1is the Most Significant Bit (MSB)Note: some authors use different index notationAn Ideal ADC is characterized at low frequencies by its static performanceXINADCnXOUTA/D ConvertersAnIdeal ADC transfer characteristic (3-bits)XINADCnXOUTREF LSBn=2X XXIN<0 0 0> <0 0 1> <0 1 0> <0 11> <1 0 0> <1 01> <1 1 0> <1 1 1>OUTXXREFXLSBXREF -XLSBC0C1C2C3C4C5C6C7 OUTn-1 n-2 0X=<d ,d,..d >A/D ConvertersAnIdeal ADC transfer characteristic (3-bits)XINADCnXOUTREF LSBn=2X X OUTX,is the interpreted value ofThe second vertical axis, labeled OUTn-1 n-2 0X=<d ,d,..d >XINOUTXXREFXLSBXREF -XLSBXREFXLSB2 XLSB3 XLSB4 XLSB5 XLSB6 XLSB7 XLSB OUTXC0C1C2C3C4C5C6C7 OUTXA/D Convertersn-30n-1n-21 REFINn-1nddddd+++..++ = 24822 XXFor this ideal ADCn n-jREFINjj=1d = + 2 XX Number of bins gets very large for n large Spacing between break points is XREF/2nand gets very small for n largeXINADCnXOUT where is small (typically less than 1 LSB)

8 Is the quantization errorand is inherent in any ADCXINOUTXXREFC0C1C2C3C4C5C6C7A/D ConvertersXINADCnXOUTT ransition PointsXINOUTXXREFC0C1C2C3C4C5C6C7XT1XT2X T3XT4XT5XT6XT7 Actual values ofXINwhere transitions occur are termed transition pointsor break points For an ideal n-bit ADC, there are 2n-1 transition points Ideally the transition points are all separated by 1 LSB --XLSB=XREF/2n Ideally the transition points are uniformly spaced In an actual ADC, the transition points will deviate a little from their ideal locationLabeling Convention: We will define the transition point XTkto be the break point where the transition in thecode output to code Ckoccurs. Thisseemingly obvious ordering of break points becomes ambiguous, though, when more than one break points cause a transition to code Ckwhich can occur in some nonideal ADCsA/D ConvertersXINADCnXOUTQ uantization Errors OUT IN-Q XXXIN Q-XLSBXT2XT3XT4XT5XT6XT7XT1 XREFM agnitude of Qbounded by XLSB for an ideal A/DXT1=XLSBXINOUTXXREFC0C1C2C3C4C5C6C7XT 1XT2XT3XT4XT5XT6XT7 XLSB2 XLSB3 XLSB4 XLSB5 XLSB6 XLSB7 XLSBA/D ConvertersXINADCnXOUTQ uantization Errors OUT IN-Q XXMagnitude of Qbounded by XLSBA nother Ideal ADCXT1=XLSB/2 XIN XLSBXINOUTXXREFC0C1C2C3C4C5C6C7XT1XT2XT3 XT4XT5XT6XT7 XLSB2 XLSB3 XLSB4 XLSB5 XLSB6 XLSB7 XLSBIs the performance of this ideal ADC really better than that of the previous ideal ADC?

9 Data Converter ArchitecturesXINADCnXOUTnXOUTDACINX Large number of different circuits have been proposed for building data converters Often a dramatic difference in performancefrom one structure to another Performance of almost all structures are identical if ideal components are used Much of data converter design involves identifying the problems associated with a given structure and figuring out ways to reduce the effects of these problems Critical that all problems that are significant be identified and solved Many of the problems are statistical in nature and implications of not solving problems are in a yield loss that may be dramaticData Converter ArchitecturesXINADCnXOUTnXOUTDACINXS trategy for discussing data converters Briefly look at some different data converter architectures Detailed discussion of performance parameters for data converters More detailed discussion of data converter architecturesData Converter ArchitecturesXINADCnXOUTnXOUTDACINXN yquist RateFlashCharge RedistributionPipelineTwo-step and Multi-StepInterpolatingAlgorithmic/Cycli cSuccessive Approximation (Register) SARS ingle Slope / Dual SlopeSubrangingFoldedInterleavedCurrent SteeringR-stringCharge RedistributionAlgorithmicR-2R (ladder)PipelinedSubrangingOver-Sampled (Delta-Sigma)Discrete-timeFirst-order/Hi gher OrderContinuous-timeDiscrete-timeFirst-o rder/Higher OrderContinuous-timeData Converter ArchitecturesXINADCnXOUTRRRRRVREFnXOUTVI NT hermometer to Binary DecoderFlashEnd of Lecture 24