ASE Technology Roadmap - asetwn.com.tw

1 ASE Technology RoadmapASE Technology RoadmapPresented by The Advanced Semiconductor Engineering GroupDec. 01. 2006 ASEK 2007 Roadmap PKG Roadmap update. SIP / PiP / POP Technology Roadmap Leadless QFN Technology Roadmap Low K / Fine Pitch Wire Bond Technology Technology Overview -- SiPPackage ItemAvailable200720082009 Package Thickness (mm)(2/3/4 die stacked) / / / / / / / of Die99 Hybrid (WB+FC) Package Height (mm) ~20X2010X10~20X20 Max. Package Size (mm)27x2721x21 Wire Bond TechnologyTri-tierTri-tierTechnologyGree nGreenPackage Thickness (mm)PKG Size (mm)TechnologyMin. Package Thickness (mm)FC+WB typeFC+WB typeFC+WBFC+ / 3 / 4 / 5 / ~20X20 WBFC+WBSCSPE utectic BumpLead free BumpWB typeFC+WB Technology Overview -- TechnologyTechnology ItemAvailable200720082009Cu WaferW/B package (um)90 Low-K65 LK65 ELK65 ELK45 ELK32 ELKIn-line (um)3030 Staggered (um)3535 Quad-tier (um)605045452020Pd platingPd platingCopper WirePlating Cu WireN/AN/APackage WLCSPBGA LaminateFlip Chip BGAT echnologyFine Pitch140120 SubstrateGreenBare Cu WireN/A25 umLeadfremePlatingSnCu / Matt Sn / SnBiPPF5-tier (um)3535 Tri-tier (um)Bump Pitch (um)Thickness (2L/4L, mm)Ball pitch (mm) ( SCSP/PiP ) Package mm LGA( mm Cap) mm LGA( mm Cap) mm LGA( mm Cap) mm LGA( mm Cap) CSP( Cap) CSP( Cap) CSP( Cap) CSP( Cap) SCSP7 Chips9 Chips9 Chips9 ChipsHybrid PkgFC+WB (Lead Free)FC+WB (Green)FC+WB (Green)FC+WB (Green)EnvironmentalRoHs/ GreenRoHs/ GreenRoHs/ GreenRoHs/ mm CSP( mm Cap) mm CSP( mm Cap) mm CSP( mm Cap) mm CSP( mm Cap)

2 PackageAvailable200720082009 Package SturctureReliabilityMSL3 @ 260 MSL2Aa @ 260 MSL2Aa @ 260 MSL2Aa @ 260 MSL2Aa @ 260 EnvironmentalRoHs/ GreenRoHs/ GreenRoHs/ GreenRoHs/ GreenInterconnectionWBWB + FCWB + FC MCMWB + FC MCMPiP Package RoadmapAFFC+WBFC+WBWB/ FCWBT echnologyWB/ FCWB/ FCWB/ FCWBT echnologyStructureStructure10X10~20X20 10X10~20X2012X1214X14 PKG Size(mm) MaxPKG Height(mm) Pitch (mm)2 die/ 1 die2 die/ 1 die2 die/ 1 die1 dieDie CountTRD PoPPKG Size (mm)PKG Height (mm)Interconnection Pitch (mm)Die Count10X10~20X2010X10~20X2010X10~ die2 die2 die/ 1 die1 dieMAP PoP200920082007 AvailablePoP TypeWB PoPFC PoPWB PoPFC PoPPoP Package RoadmapLeadless QFN Package & Technology RoadmapTechnologyItemAvailableHVM2007200 82009 Package Size (mm)3x3~8x812L~ 8L7x7NA~19x19 Single CutLead Count8 ~ 64~136~164~208 Package Thickness (mm) Non-EPQFN-EPQFN-EP & QFN Non-EPDFN / SONI nternal QualDFN / SONDFN / SON Dual RowMCM2 die stack3 die stackFC+WBDouble cutTri-RowMulti RowFlip Chip QFNMSL1 (mm)FC+WB QFN12x12 SQFN Saw ProcessDouble cut + High speed3x3 ~ 9x9~12x12~14x14 Single RowDual RowN/AFCQFN9x910x10 TechnologySingle CutPackage OfferingIC Feature Size (um) Wire Bond pad Pitch (um)(Single-In-Line) Wire Bond Pad Pitch (um) (2 Row Staggered) Wire Bond Pad Pitch (um)(Tri-Tier) Wire Bond pad pitch (um) ( Quad-Tier ) Wire Bond pad pitch (um) ( 5-Tier )605045 40 3580/4070/3560/30 50/25 40/2090/4580/4070/35 60/30 50/25 100/50 90/45 80/40 70/3060/30100/50 90/45 80/40 70/3060/30 Leading-Edge Fine-Pitch Capabilities In-Line: 40um, Staggered: 50um, Tri-Tier: 50um, Quad-Tier: 60um, 5-Tier.

3 70 um Low k & Copper wafer capabilities Pitch Wire BondingBase on customer volumeASE engineering study Wafer ChipQFPBGAFlip ChipQFPBGAFlip ChipQFPY2007H1 BGAY2007H1 Flip ChipY2007H2 QFPY2008H2 BGAY2008H2 Flip Package Development Status