June 25 th, 2013 1 - The ConFab

1 June 25th, 2013. 1. Outline Introduction Electronic trend toward more system integration Current OSAT Role for System Integration SiP (Modules). Expanding Role to for system integration: a new approach Large are processes as cost effective alternatives Summary 2. Mobile Devices and Internet Lead the Growth of Electronics W/W Smartphone Shipment & FCST to 2016 W/W Tablet Shipment & FCST to 2016. Shipment (M of Units). Shipment (M of Units). 320 +400%. 1,600 +100% Tab let 283. Smartphone 1,405. YoY. YoY. +279%. 1,200 +75%. 240 +300%. +62%. +46%. 800 722 +50% 160 +200%. 128. 495. 72 +78%. 400 305 2012~2016 +25% 80 2012~2016 +100%. CAGR CAGR. 19. +18% +22%. 0 +0% 0 +0%. 2010 2011 2012 2016 2010 2011 2012 2016. W/W Sever Shipment & FCST to 2017. Production Units (K) CAGR. Application 2011 2012 2013 2014 2015 2016 2017 2013~17. Server 50 56 60 63 66 72 81 - - High End Server 3,158 3,542 4,027 4,447 4,928 5,365 5,709 Low End Subtotal 3,208 3,599 4,087 4,509 4,994 5,437 5,789 Source : IDC (phone & tablet), Gartner (server), Mar.

2 2013. 3. Industry is In System Integration Era Multiple functions (systems) are Integrated into a single system 4. Mobile Devices Induced Side Effects' Need More Innovations 1. Head down syndromes': personal health and public safety hazards 2. Carrying extra weight: mobile power (charger, battery) market CAGR ~10%. 5. Next Generation of Electronics Need More System Integration The future electronic device: in form of smart' wearable electronics ? Sony Audex In movie only Google Smart Glass Smart Watch Smart Jacket Smart Helmet Whatever it may be, all need more smart system integration toward: Better Performance (more Electronics: FinFET/ FDSOI, EUV, 450mm fab, 3 DIC. functionality, higher speed, less power). Display: OLED, in/on cell Smaller Size (volume), lighter weight touch panel Battery: ? (Wireless charging, Affordable Cost energy harvest, fuel cell ).

3 6. OSAT and the Roles OSAT(S): Outsourced Semiconductor Assembly and Testing (Service). I. IDM : Integrated Device Manufacturer System IC. Houses IC. IC Fab Packaging Design & Testing 2. OEM. 4. OEM/ODM (SiP). 1. OEM. IC Design & IC Packaging Sales IC Fab & Testing (fabless com) (Foundries) 3. OEM (OSAT). (turnkey). 7. SiP Module Development for Internet of Things . WICED (WiFi+MCU) WICED SiP. COB Solution solution BLE (Bluetooth Low Size : 25x19 mm2 Size : 10x10 mm2 Energy) COB Solution BLE SiP solution Size : 18x12 mm2 Size : mm2. 79% area reduction! 81% area reduction! Include WiFi + MCU Include BLE, EEPROM, Antenna Component Count : 54 Component Count : 28. Process : wafer thinning, stack Die Process : stack die on passives, on FC , MUF Antenna on Module, Molding Application : Industrial control, toys, Application : Consumer Devices, Toys, health care, fitness, camer, Wireless mobile phone accessories Video / Audio 8.

4 SiP Module w/ Various Package Structure Structure SiP Module Product Key Process WiFi MIMO/BT Module, WiMAX. High Density SMT Process FC Base MUF + Sputter Coating Underfill + Metal Shielding IPD for RF Components WiFi+BT / GPS. SMT. DB/WB Base DB/WB. MUF. WiFi + BT / WiFi + MCU. SMT. DB/WB. Stack/Hybrid Stack Die Assemble IPD Interposer MUF. Dual-Side Assembly Antenna On BT BLE / WiFi Module SMT / FC / DB / WB / MUF. Metal Lid Shielding Optimization Metal Shielding for EMI/Thermal / Coating Metal Coating for EMI. 9. Simulations Capability on SiP Modules Simulations Thermal Stress Electrical Critical Thermal Max. Warpage S Parameter Temperature Contour Solder Fatigue Life Signal / Power Integrity Flotherm Mold Flow Antenna ANSYS ANSYS HFSS, Power SI. LS-DYNA HSPICE, ADS. Q3D, TPA. 11a/b/g/n MIMO + 11b/g + BT SiP Module BT Antenna SiP Module 1. 10. 0.

5 TSV based IC: Product Drought* ? Memory Memory IC Logic 3D IC Memory TSI Logic Substrate Substrate with Through Silicon Interposer (TSI) TSV in Logic and DRAM stack 3D Package Content Application Major Concerns for IC Product launching Logics /(on) TSI FPGA/ High speed Cost (Homogeneous Integration) logic Logic + Analogs+../ TSI System partitioning (& Cost & TSI design (Heterogeneous Integration) aggregation). Logic (Processors)+ Computing Cost, DRAM stack DRAM stacks/ TSI availability 3D Memory Stack Wide IO DRAM, No consensus on HMC mainstream (vs. DDR4). yet, Cost 3D Wide IO DRAM on Mobile Cost /design/ thermal Logic Communication issues, DRAM avialability *: No product announcement since FPGA/DRAM (2010). Confidenti 11. is Cost Effective Solution for System Integration Logic1 Analog Memo Logic1 ry Logic 2 eMemory Vs. Logic1 Logic1 Logic 2. SoC (Monolithic IC) with Multiple ICs Integrated with TSI.

6 High end Fab tech node ( ). Cost Benefit of IC. Logic 1: High speed Smaller die (higher yield). processor Less on die routing (less metal layers). Logic 2 Legacy fab & tech. node, IP re-used Analog IP re-used, legacy fab tech/ node, higher degree of device optimization Memory Integrate with commonality memory whole system cost benefit > TSI cost adder Plus better system performance gain 12. IC TSI Key Process & Business Models OSAT/ Fndy OSAT TSI. Key Process Modules Foundry collaboration turn key 1. TSV formation Other (wf un-thinned). TSI Front Side 2. Fine Pitch RDLs Foundries x3. Enabled (>2 layers, metal line width). 3. Micro pad (UBM/Cu/ Ni/ Au) OSAT x5. DB/ Reflow/ UF/ Molding/ Grinding n/a 4a. Temporary Carrier Bonding CoWoS TM. (thinned wf on glass). 5. Wafer thinning (<100 um). TSI backside TSMC SPIL. 7. Backside Via Reveal module 8. Backside RDL (optional) OSAT.

7 X5. 9. C4 bumping Temporary Carrier Debonding+DS. Assembly process (DB/RFL/UF- n/a repeats). 1um Line by Cu Dual Damascene: Yes, we can do it! 14. Benefits of SPIL's Turnkey Service Another alternative to broaden the choices of supply chain, market make decision Time to market: single integrator of TSI (- need some learning curve for Cu DD). Flexibility: OSAT are used to accept IC wafers from everyone Metal line width/ thickness can tailor to the need, not just of the shelf from the library Potential cost competiveness: due to OSAT cost infrastructure 15. Chip Packaging Interaction: 3 DIC Co-design Flow Confidenti 16. IC Pose No Technology Barrier Micro joint TSI TSV. C4 joint Top die Top die TSI. TSI. Substrate Substrate All process technologies of completing , with foundry collaboration model, have been established 17. DRAM 3D Stacking, No Problem Demonstration in ITRI.

8 4 die 3D DRAM Stack is achieved in SPIL. 18. Competition for Low Cost IC. Si Interposer (with TSV) Organic Interposer (fine pitch laminate substrate). Core Material (CTE) Silicon (3ppm/K) Organic (4ppm/K). Core Thickness 100 150~400 . 3 Min. Metal line Width < 1 (all the way to nm) 2 @ 2015. Structure Asymmetry (n+1) Symmetry (n+n). Warpage control Achievable Yield TBD. Core through hole Laser via/ Mechanical DRIE. process drilling PECVD/ DRIE/ PVD /Cu Plating Lamination / Laser/ E'less Metallization process /CMP Cu/ Cu plating (IC fab process) (PCB process). 400 mm x500 mm Process area 300mm Si wafer (now only 200mm x 250mm). Gross die 66 240. (die size 26mm x 32mm). Large area process is key to low cost 19. Biggest Piece of Fan Out Packaging Ever Built WLFO. 12 Panel 12 . Carrier size PKG size PKG Q'ty Ratio 12" (300mm) 723 1X. 9x9mm Panel (370*470mm) 1862 20.

9 SPIL's Panel Fan-Out Packaging (P-FO). 470mm PKG Information PKG Size: 9x9 mm Die Size: 6x6 mm I/O # : 356. 370mm 21. P-FO Package is the base of thin PoP. For LPDDR4 DRAM For Wide I/O 2 DRAM. 3L RDL : Btm 2L+ Top 1L 4L RDL : Btm 2L+ Top 2L. (5um/5um L/S, TPV 50um). Low cost alternative to TSV 3 DIC for mobile application Confidential 22. Summary Smart phones and tablets have led the growth of electronics, higher degree of system integration is needed toward next generation of electronic devices SPIL, as a leading OSAT, would participate and expand our role toward more solutions for system integration. Developed fine pitch RDL capability, with Cu/oxide dual damascene process, to enable a TSI turnkey service, provide the alternatives, and broaden the supply chain choices Developed the large area packaging, a unprecedented Panel Fan out packaging is demonstrated, provide the full potential to offer a thin PoP solution and as TSV 3 DIC alternatives Confidenti 23.

10 Thanks for your attentions~. Thanks for your attention !! 24 Confidential 24.