Panel Discussion: Advanced Packaging - The ConFab

1 Dr. Steve Bezuk Senior Director IC Packaging Engineering Qualcomm Technologies, Inc. Panel discussion : Advanced Packaging PAGE 1. Technical Challenges of Packaging (Mobile Focus). Materials Thermal Die materials Poor Thermal Paths Low K and Extreme Low K Dielectrics No Air Flow, Closed System Fine Pitch Interconnects (<100mm) Substrate materials engineered for: Electrical Modulus, fracture toughness, CTE, Tg, Signal Integrity shrinkage, cure temperature and kinetics, adhesion to multiple materials, dielectric Power DistribuLon properties (frequency dependence).

2 FuncLonal ParLLoning Mechanical Ultra thin die ( 100mm) Evolution of Si nodes in last 5 yrs CTE Mismatch 14/16 7. Warpage Control 28nm 20nm nm 10 nm nm Preserving Si Strain Engineering 1st gen 2nd gen 3rd gen FINFET FINFET FINFET. 2017 QUALCOMM Incorporated. All rights reserved PAGE 2. Interconnect Trends for Packages FC Interconnect using SOP Fine Pitch FC used in mobile devices DieSOP. Transition for CuBOL ETS. Finer Pitches FC ( 130 um) CuBOL/ETS (>100 um) ETS(>60-80 um) TCFC ( 80 um). - Fine pitch Cu pillar interconnect - Mass reflow most common and cheapest joining process - Capillary and molded underfills are used - TCFC and Laser Assisted - Lower stress attach PAGE 3.

3 2017 QUALCOMM Incorporated. All rights reserved - Ability to handle warped substrates Current Mobile Packaging for Apps Processors High End Processors Mid End Processors Low End Processors Pseudo-Embedded POP packages MCeP (Shinko/. Amkor) + +. Memory Memory FO Structure InFO (TSMC). Molded Laser PoP (MLP). with or w/o die exposed 2017 QUALCOMM Incorporated. All rights reserved PAGE 4. The Quest for smaller form factor and higher integration FO-WLP. Eliminates die interconnect (bump and wirebonds) and substrate Finer pitches than substrate based technology Substrate technology 10/10um L/S with 7/7um L/S in development FO technology 10-15um L/S common, 2/2um L/S in LVM.

4 Shorter interconnects = Lower parasitics Eliminate interconnect stress and ELK crack delamination issues Batch Packaging process like WLP, but can be with KGD. Potential SiP, Multi-die, 3D Solution Can improve thermal characteristics Larger Panel batch processing in development to lower cost Challenges in patterning, sputtering, plating, and metrology over large format Modules Higher component density saves PWB area Finer component pitches than standard SMT line Embedded devices enables 3D. and higher D's Shorter interconnects = Lower parasitics Interconnect pitches approaching wafer BEOL.

5 2/2um L/S in LVM, 1/1um L/S in development Multiple die or Split die architectures Can require in 2/2um L/S or better Improved power dissipation 2017 QUALCOMM Incorporated. All rights reserved PAGE 5. Wafer Batch Processed Package Evolution WLP Face Down WLP with Face Up WLP/ Face Down Face Up FOWLP. FOWLP Sidewall Prot. FOWLP FOWLP POP (InFO). Time Features and - Lowest cost - Cost e ec2ve for - More robust - Flat surface to - Thinner POP - Flat surface for Bene ts solu2on if die requiring handling, Not paBern RDL. possible paBerning RDL. applicable some fan out prone to edge Finer pitch compared to Finer pitch Pillars - Finer pitch - Lower parasi2cs cracking possible substrate based for POP rou2ng than - Finer pitch - Mold protec2on connec2on than substrates rou2ng than over die surface solder balls substrates Challenges - Rel limits die size - Yield challenges - Increases cost - Requires growth - Cost For 2+ RDL - Cost for 2+ RDL - Handling issues because die rst over WLP of Cu pillar on die - Cost to grow Cu for EMS - 2+ layers of RDL increasing cost pillars for POP - Low K makes more

6 Expensive over face down worse than substrate FOWLP pkg. Applica2ons - Devices that I/O - Many FC - Same as WLP - Same as FOWLP, - Apps processor - Apps processor boundary applica2ons can WLP, sidewall for high end for high end port protected WLP phones phones - Mul2 chip modules 2017 QUALCOMM Incorporated. All rights reserved PAGE 6. Advanced Packages for Multichip, Processors, GPUs and FPGA. TSI FOCoS SWIFT Photo-Defined EMIB. CoWoS, CoW, CoS Fan Out Chip on Organic Interposer Substrate (POI). Suppliers TSMC, Multiple ASE Amkor Shinko Intel OSATS. Features Si Interposer Die first face down FO Conventional RDL Advanced PID Substrate Si Bridge Embedding Glass Interposers in construction Die last assembly Die last assembly Laser SRO/ Mixed development for Leverages HVM AOI inspected RDL AOI Inspected RDL Bump improve electrical processes of standard In Dev.

7 In Dev. Known Good Si Bridge performance by GaTech FOWLP but fine pitch In LVM. Die first or last assembly RDL. depending on process In Dev. flow In LVM. Assembly Complexity Si Interposer FO processes+ PKG to RDL+ Chip Joining Conventional Chip Joining Conventional Chip Joining +Substrate Assembly Substrate Assenly + PKG to Substrate only only Assembly Multi-die Integration Multi-die and mix node Multi-die and mix node Multi-die and mix node Multi-die and mix node Multi-die and mix node and mix pitch technology and mix pitch technology and mix pitch technology and mix pitch technology and mix pitch technology integration integration integration integration integration 2017 QUALCOMM Incorporated.

8 All rights reserved PAGE 7.