USBXpress™ Family 1.2 Specification) - Silicon Labs

1 USBX press FamilyCP2102N Data SheetThe CP2102N devices, part of the USBX press Family , are de-signed to quickly add USB to your applications by eliminatingfirmware complexity and reducing development highly-integrated USB-to-UART bridge controllers provide a simple solution forupdating RS-232 designs to USB using a minimum of components and PCB includes a USB full-speed function controller, USB transceiver, oscillator,and Universal Asynchronous Receiver/Transmitter (UART) in packages as small as 3mm x 3 mm. No other external USB components are required for development. All cus-tomization and configuration options can be selected using a simple GUI-based config-urator. By eliminating the need for complex firmware and driver development, theCP2102N devices enable quick USB connectivity with minimal development is ideal for a wide range of applications, including the following:KEY FEATURES No firmware development required Simple GUI-based configurator Integrated USB transceiver; no externalresistors required Integrated clock.

2 No external crystalrequired USB full-speed compatible Data transfer rates up to 3 Mbaud USB Battery Charger Detection (USB Specification) Remote wakeup for waking a suspendedhost Low operating current : mA Royalty-free Virtual COM port drivers POS terminals USB dongles Gaming controllers Medical equipment Data loggersExternal RS-232 transceiver or UART circuitryExternal circuitry for USB suspend statesCP2102N48 MHz OscillatorUSB Battery Charger DetectRemote WakeupUSB ConnectorExternal battery charging circuitryVoltageRegulatorUSB FunctionController512 byte RX Buffer960 byte Configuration MemoryUARTH ardware HandshakingRS485 USBT ransceiver512 byte TX BufferFeature is related to:UARTUSBO verall | Building a more connected 1. Feature List and Ordering Information2102N A RTape and Reel (Optional)Package Type QFN20, QFN24, or QFN28 Firmware RevisionHardware Revision01 CPGQFN20 Temperature Grade 40 to +85 C (G) Silicon Labs Xpress Product LineUSBX press Family , USB-to-UART BridgeFigure CP2102N Part NumberingThe CP2102N devices have the following features: Single-Chip USB-to-UART Data Transfer Integrated USB transceiver; no external resistors required Integrated clock.

3 No external crystal required Internal 960-byte programmable ROM for vendor ID, prod-uct ID, serial number, power descriptor, release number,and product description strings On-chip power-on reset circuit On-chip voltage regulator V output Pin compatible with CP2101/2/9 (QFN28 package) Pin compatible with CP2104 (QFN24 package) USB Function Controller USB Specification compliant; full-speed (12 Mbps) USB suspend states supported via SUSPEND pins USB Battery Charger Detection (USB BCS Specifica-tion) Remote wakeup for waking a suspended host Single power supply of to V or to V Universal Asynchronous Receiver/Transmitter (UART) All handshaking and modem interface signals Data formats supported Data bits 5, 6, 7, and 8 Stop bits 1, , and 2 Parity odd, even, mark, space, no parity Baud rates.

4 300 baud to 3 Mbaud 512 byte receive buffer 512 byte transmit buffer Hardware or Xon/Xoff handshaking supported Virtual COM Port Device Drivers Works with existing COM port Applications Supported on Windows, Mac, and Linux Royalty-free distribution license Direct Driver Support Royalty-free distribution licenseTable Product Selection GuideOrderingPart NumberGPIOsBattery Charger DetectSeparate VIOand VDD PinsPb-free(RoHS Compliant)Temperature RangePackageCP2102N-A02-GQFN287 Yes Yes-40 to +85 CQFN28CP2102N-A02-GQFN244 YesYes-40 to +85 CQFN24CP2102N-A02-GQFN204 Yes-40 to +85 CQFN20 with the same ordering part number may have different types of pin 1 indicators. However, all of these variants can usethe same landing diagram as long as the recommended landing diagram instructions are followed.

5 CP2102N Data SheetFeature List and Ordering | Building a more connected | 2 Table of Contents1. Feature List and Ordering Typical Connection Battery Charger Electrical Electrical Recommended Operating Power Reset and Supply Configuration Internal 5 V Voltage USB Thermal Absolute Maximum Typical Performance Functional USB Function Controller and Universal Asynchronous Receiver/Transmitter (UART) Baud Rate Sending Break Additional General Purpose Input/Outputs (GPIO).. Dynamic Output Battery Charging (CHREN, CHR0, and CHR1).. Remote Wakeup (WAKEUP).. Clock Output (CLK).. Hardware Handshaking (RTS and CTS).. Software Data Throughput Transmit and Receive LED Toggles (TXT and RXT).

6 Modem Control (DSR, DTR, DCD, RI).. RS485 (RS485).. Receiver Virtual COM Port (VCP) USBX press Customization and | Building a more connected | Device Pin CP2102N QFN28 Pin CP2102N QFN24 Pin CP2102N QFN20 Pin QFN28 Package QFN28 Package QFN28 PCB Land QFN28 Package QFN24 Package QFN24 Package PCB Land Package QFN20 Package QFN20 Package QFN20 PCB Land QFN20 Package Relevant Application Revision | Building a more connected | 42. Typical Connection PowerIn all cases, a 1 k pull-up on the RSTb pin is recommended. This pull-up should be tied to VIO on devices that have it. On deviceswhere VIO is connected to VDD or devices that do not have VIO, this pull-up should be tied to VDD.

7 The RSTb pin will be driven lowduring power-on and power failure reset figure below shows a typical connection diagram for the power pins of the CP2102N devices when the internal regulator is usedand USB is connected (bus-powered).CP2102N F and F bypass capacitors required for each power pin placed as close to the pins as V (out)VDDUSB 5 V (in)RSTbVIOF igure Connection Diagram with Voltage Regulator Used and USB Connected (Bus-Powered)The figure below shows a typical connection diagram for the power pins of the CP2102N devices when the internal regulator is usedand USB is connected (self-powered).CP2102N F and F bypass capacitors required for each power pin placed as close to the pins as V (out) V (in)RSTbVIOF igure Connection Diagram with Voltage Regulator Used and USB Connected (Self-Powered)CP2102N Data SheetTypical Connection | Building a more connected | 5 The figure below shows a typical connection diagram for the power pins of the CP2102N devices when the internal 5 V regula-tor is not V (in)

8 F and F bypass capacitors required for each power pin placed as close to the pins as kohmFigure Connection Diagram with Voltage Regulator Not UsedCP2102N Data SheetTypical Connection | Building a more connected | Battery Charger DetectThe CP2102N Battery Charger Detect notifies an external battery charger the amount of current available from the USB figure below shows an example connection diagram for external battery charging circuitry. If using an external battery charging IC,consult the data sheet for more information about the specific recommended connection DeviceD+GNDVREGIND-USBC onnectorVBUSD+Signal GNDD-VBUSCHR1 ( A)CHR0 (500 mA)CHREN (100 mA)External Battery Charging ICSETICENSP0503 BAHT or equivalent USB ESD protection diodes(Recommended) k k Figure Battery Charging Connection DiagramCP2102N Data SheetTypical Connection | Building a more connected | USBThe figure below shows a typical connection bus-powered diagram for the USB pins of the CP2102N devices including ESD protectiondiodes on the USB : There are two relevant restrictions on the VBUS pin voltage in self-powered and bus-powered configurations.

9 The first is the ab-solute maximum voltage on the VBUS pin, which is defined as VIO + V in Table Absolute Maximum Ratings on page 15. Thesecond is the Input High Voltage (VIH) for VBUS to detect when the device is connected to a bus, which is defined as VIO V inTable GPIO on page 13. A resistor divider (or functionally-equivalent circuit) on VBUS is required to meet these specifications andensure reliable device operation. In this case, the current limitation of the resistor divider prevents high VBUS pin leakage current, eventhough the VIO + V specification is not strictly met while the device is not powered. CP2102N DeviceUSBD+GNDVREGIND-USBC onnectorVBUSD+Signal GNDD-SP0503 BAHT or equivalent USB ESD protection diodes(Recommended) k k Figure Bus-Powered Connection Diagram for USB PinsCP2102N Data SheetTypical Connection | Building a more connected | 8 The figure below shows a typical connection self-powered diagram for the USB pins of the CP2102N devices including ESD protectiondiodes on the USB : There are two relevant restrictions on the VBUS pin voltage in self-powered and bus-powered configurations.

10 The first is the ab-solute maximum voltage on the VBUS pin, which is defined as VIO + V in Table Absolute Maximum Ratings on page 15. Thesecond is the Input High Voltage (VIH) for VBUS to detect when the device is connected to a bus, which is defined as VIO V inTable GPIO on page 13. A resistor divider (or functionally-equivalent circuit) on VBUS is required to meet these specifications andensure reliable device operation. In this case, the current limitation of the resistor divider prevents high VBUS pin leakage current, eventhough the VIO + V specification is not strictly met while the device is not powered. CP2102N DeviceUSBD+GNDVBUSD-USBC onnectorVBUSD+Signal GNDD-SP0503 BAHT or equivalent USB ESD protection diodes(Recommended) k k Figure Self-Powered Connection Diagram for USB PinsCP2102N Data SheetTypical Connection | Building a more connected | 93.