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AN1107: Si5332 Power Supply Noise Rejection - Silicon Labs

an1107 : Si5332 Power Supply NoiseRejectionThis application note showcases the Power Supply Noise Rejection (PSNR) performanceof Supply Noise are a significant problem in high performance clocking. A clock cir-cuit that is dependent on a voltage source will be affected by the Noise of that source inthe following Noise (or variation) in voltage will add Noise to the clock signal voltage. Sincecrossing point times are referenced to a crossing voltage , the voltage Noise willmanifest as timing Noise in the Power Supply gets uplinked (modulated) by the internal oscillator inthe PLL causing a significant phase Noise the two issues above, #2 is most Si5332 both the problems above are dealt with in the following Power Supply to the output buffer circuits are regulated by sophisticated (andindependent)

AN1107: Si5332 Power Supply Noise Rejection This application note showcases the power supply noise rejection (PSNR) performance of Si5332. Power supply noise are a significant problem in high performance clocking. A clock cir-cuit that is dependent on a voltage source will be affected by the noise of that source in the following ways:

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Transcription of AN1107: Si5332 Power Supply Noise Rejection - Silicon Labs

1 an1107 : Si5332 Power Supply NoiseRejectionThis application note showcases the Power Supply Noise Rejection (PSNR) performanceof Supply Noise are a significant problem in high performance clocking. A clock cir-cuit that is dependent on a voltage source will be affected by the Noise of that source inthe following Noise (or variation) in voltage will add Noise to the clock signal voltage. Sincecrossing point times are referenced to a crossing voltage , the voltage Noise willmanifest as timing Noise in the Power Supply gets uplinked (modulated) by the internal oscillator inthe PLL causing a significant phase Noise the two issues above, #2 is most Si5332 both the problems above are dealt with in the following Power Supply to the output buffer circuits are regulated by sophisticated (andindependent)

2 Internal voltage regulator circuits that isolate the clock output buffercircuit from the Noise on the Power Supply voltages provided by the Power Supply to internal digital, input buffer and analog circuitry all have dedi-cated and independent internal voltage regulator circuits that isolate the internal os-cillator from the Noise on the Power Supply voltages provided by the , the Si5332 clock generator can provide a clock signal that is immune to powersupply Noise from the application note provides a report on the immunity of Si5332 to Supply Noise interms to Noise to Noise frequencyKEY POINTS Power Supply Noise Rejection Switch mode supplies and | Building a more connected Table of Contents1. Experiment Set Up for PSNR Si5332 PSNR | Building a more connected | 21.

3 Experiment Set Up for PSNR MeasurementsThe figure below shows the experiment setup for PSNR measurement. An AWG (Arbitrary Waveform Generator) was used to controlthe Noise amplitude and the Noise frequency. This Noise was coupled into the DUT through a bias-tee arrangement. The effect of thisnoise was measured as phase Noise on a signal source analyzer. The study analyzes the tones induced by the Supply Noise on phasenoise and calculates the effective jitter including the spurious tones induced due to the Noise was also measured and used to calculate PSRR ( Power Supply Rejection Ratio) using thefollowing Power of the spurious tone is measured in the phase Noise plot as = Ptone Pcarrier , Pcarrier is the carrier Power sensed by the signal source = Ptone_in_dbm Pnoise , where Pnoise is injected from the AWG (shown in the figure below).

4 , VDDO nodesCLK+CLK-Signal Source AnalyzerBias Tee for Noise injectionFigure PSNR Set UpAN1107: Si5332 Power Supply Noise RejectionExperiment Set Up for PSNR | Building a more connected | 32. Si5332 PSNR PerformanceThe Si5332 PSNR performance is shown in the table below as the effect of Supply Noise on jitter. The following figure shows this samedata Jitter Vs Power Supply Noise for VPhase jitter with no Noise = 232 fs, carrier Power = dBm, Noise amplitude = 100 mVPower Supply Noise frequency (KHz) Power of spurious tone (dBC)RMS jitter (fs) Jitter vs Power Supply NoiceAN1107: Si5332 Power Supply Noise RejectionSi5332 PSNR | Building a more connected | 4 The PSRR performance is shown in the table Supply Noise fre-quency (KHz) Power of spurious tone(dBC) Power of the tone(dBm) Power of the Noise fre-quency (dBm)PSRR (dB)Phase jitter with no Noise = 224 fs, carrier Power = dBm, Noise amplitude = 100 : Si5332 Power Supply Noise RejectionSi5332 PSNR | Building a more connected | 53.

5 ConclusionThe Si5332 provides excellent PSRR the Power Supply Noise amplitude is less than or equal to 100 mV (even with Noise , the VDD level should not drop below V), thePSRR is excellent over a wide band of Noise frequencies. Hence, the PSRR performance applies both for sinusoidal Noise sources andnoise from switching regulators (the switching Noise is a wide band signal and the study demonstrates Si5332 PSRR over a wide rangeof Noise frequencies).The Supply filtering recommended (given the excellent PSRR) is a F and 1 F, decoupling capacitance on each VDD node (asclose to the VDD node as possible), because these capacitance are essential to reduce switching Noise from the Si5332 part and act ascharge buckets for the Si5332 output : Si5332 Power Supply Noise | Building a more connected | 6 Laboratories West Cesar ChavezAustin, TX 78701 USAC lockBuilder ProOne-click access to Timing tools, documentation, software, source code libraries & more.

6 Available for Windows and iOS (CBGo only). and Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein.

7 This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such InformationSilicon Laboratories Inc. , Silicon Laboratories , Silicon Labs , SiLabs and the Silicon Labs logo , Bluegiga , Bluegiga Logo , Clockbuilder , CMEMS , DSPLL , EFM , EFM32 , EFR, Ember , Energy Micro, Energy Micro logo and combinations thereof, "the world s most energy friendly microcontrollers", Ember , EZLink , EZRadio , EZRadioPRO , Gecko , ISOmodem , Micrium, Precision32 , ProSLIC , Simplicity Studio , SiPHY , Telegesis, the Telegesis Logo , USBX press , Zentri and others are trademarks or registered trademarks of Silicon Labs.

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