SN54/74LS192 SN54/74LS193 PRESETTABLE BCD/DECADE …

1 5-1 FAST AND LS TTL DATAPRESETTABLE BCD/DECADEUP/DOWN COUNTERPRESETTABLE 4-BIT BINARYUP/DOWN COUNTERThe sn54 / 74ls192 is an UP/DOWN BCD Decade (8421) Counter and theSN54/ 74ls193 is an UP/DOWN MODULO-16 binary Counter. SeparateCount Up and Count Down Clocks are used and in either counting mode thecircuits operate synchronously. The outputs change state synchronous withthe LOW-to-HIGH transitions on the clock Terminal Count Up and Terminal Count Down outputs areprovided which are used as the clocks for a subsequent stages without extralogic, thus simplifying multistage counter designs.

2 Individual preset inputsallow the circuits to be used as programmable counters. Both the ParallelLoad (PL) and the Master Reset (MR) inputs asynchronously override theclocks. Low Power .. 95 mW Typical Dissipation High Speed.. 40 MHz Typical Count Frequency Synchronous Counting Asynchronous Master Reset and Parallel Load Individual Preset Inputs Cascading Circuitry Internally Provided Input Clamp Diodes Limit High Speed Termination EffectsNOTE:The Flatpak versionhas the same pinouts(Connection Diagram) asthe Dual In-Line DIAGRAM DIP (TOP VIEW)14131211109123456716158 VCCP1P0 MRTCDTCUP2 PLP3Q1Q0 CPDCPUQ2Q3 GNDPIN NAMESLOADING (Note a)HIGHLOWCPUCPDMRPLPnQnTCDTCUC ount Up Clock Pulse InputCount Down Clock Pulse InputAsynchronous Master Reset (Clear) InputAsynchronous Parallel Load (Active LOW) InputParallel Data InputsFlip-Flop Outputs (Note b)Terminal Count Down (Borrow) Output (Note b)Terminal Count Up (Carry) Output (Note b) ( ) ( ) ( ) :a.

3 1 TTL Unit Load ( ) = 40 A mA The Output LOW drive factor is for Military (54) and 5 for Commercial (74)b. Temperature BCD / DECADEUP / DOWN COUNTERPRESETTABLE 4-BIT BINARYUP / DOWN COUNTERLOW POWER SCHOTTKYJ SUFFIXCERAMICCASE 620-09N SUFFIXPLASTICCASE 648-08161161 ORDERING INFORMATIONSN54 LSXXXJC eramicSN74 LSXXXNP lasticSN74 LSXXXDSOIC161D SUFFIXSOICCASE 751B-03 LOGIC SYMBOLVCC = PIN 16 GND = PIN 85432671291011511 CPDQ0Q1Q2Q3 TCDP3P2P1P0 PLCPUTCU13MR145-2 FAST AND LS TTL DATASN54/ 74ls192 sn54 / 74ls193 STATE DIAGRAMSLS192 LOGIC EQUATIONSFOR TERMINAL COUNTLS192LS193 COUNT UPCOUNT DOWN012345678910111213141501234567891011 12131415 TCU = Q0 Q3 CPUTCD = Q0 Q1 Q2 Q3 CPDLS193 LOGIC EQUATIONSFOR

4 TERMINAL COUNTTCU = Q0 Q1 Q2 Q3 CPUTCD = Q0 Q1 Q2 Q3 CPDLOGIC DIAGRAMSVCC = PIN 16 GND = PIN 8 = PIN NUMBERSLS192P0P1P2P3 TCU(CARRYOUTPUT)Q0Q1Q2Q3MR(CLEAR)(DOWNCO UNT)CPD(UP COUNT)CPU(LOAD)PL12673459111210131514 TCD(BORROWOUTPUT)SDQQCDTSDQQCDTSDQQCDTSD QQCDT5-3 FAST AND LS TTL DATASN54/ 74ls192 sn54 / 74ls193 LOGIC DIAGRAMS (continued)VCC = PIN 16 GND = PIN 8 = PIN NUMBERSLS193P0P1P2P3Q0Q1Q2Q3MR(CLEAR)(DO WNCOUNT)CPD(UP COUNT)CPU(LOAD)PL12673459111210131514 SDQQCDTSDQQCDTSDQQCDTSDQQCDTTCU(CARRYOUT PUT)TCD(BORROWOUTPUT)5-4 FAST AND LS TTL DATASN54/ 74ls192 sn54 / 74ls193 FUNCTIONAL DESCRIPTIONThe LS192 and LS193 are Asynchronously PresettableDecade and 4-Bit binary Synchronous UP / DOWN (Revers-able) Counters.

5 The operating modes of the LS192 decadecounter and the LS193 binary counter are identical, with theonly difference being the count sequences as noted in theState Diagrams. Each circuit contains four master/slaveflip-flops, with internal gating and steering logic to providemaster reset, individual preset, count up and count flip-flop contains JK feedback from slave to mastersuch that a LOW-to-HIGH transition on its T input causes theslave, and thus the Q output to change state. Synchronousswitching, as opposed to ripple counting, is achieved bydriving the steering gates of all stages from a common CountUp line and a common Count Down line, thereby causing allstate changes to be initiated simultaneously.

6 A LOW-to-HIGH transition on the Count Up input will advance the count by one;a similar transition on the Count Down input will decrease thecount by one. While counting with one clock input, the othershould be held HIGH. Otherwise, the circuit will either count bytwos or not at all, depending on the state of the first flip-flop,which cannot toggle as long as either Clock input is Terminal Count Up (TCU) and Terminal Count Down(TCD) outputs are normally HIGH. When a circuit has reachedthe maximum count state (9 for the LS192, 15 for the LS193),the next HIGH-to-LOW transition of the Count Up Clock willcause TCU to go LOW.

7 TCU will stay LOW until CPU goesHIGH again, thus effectively repeating the Count Up Clock,but delayed by two gate delays. Similarly, the TCD output willgo LOW when the circuit is in the zero state and the CountDown Clock goes LOW. Since the TC outputs repeat the clockwaveforms, they can be used as the clock input signals to thenext higher order circuit in a multistage circuit has an asynchronous parallel load capabilitypermitting the counter to be preset. When the Parallel Load(PL) and the Master Reset (MR) inputs are LOW, informationpresent on the Parallel Data inputs (P0, P3) is loaded into thecounter and appears on the outputs regardless of theconditions of the clock inputs.

8 A HIGH signal on the MasterReset input will disable the preset gates, override both Clockinputs, and latch each Q output in the LOW state. If one of theClock inputs is LOW during and after a reset or load operation,the next LOW-to-HIGH transition of that Clock will beinterpreted as a legitimate signal and will be SELECT TABLEMRPLCPUCPDMODEHXXXR eset (Asyn.)LLXXP reset (Asyn.)LHHHNo ChangeLHHC ount UpLHHC ount DownL = LOW Voltage LevelH = HIGH Voltage LevelX = Don t Care= LOW-to-HIGH Clock Transition5-5 FAST AND LS TTL DATASN54/ 74ls192 sn54 / 74ls193 GUARANTEED OPERATING RANGESS ymbolParameterMinTypMaxUnitVCCS upply Ambient Temperature Range5474 550252512570 CIOHO utput Current High54, 74 Current CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

9 SblPLimitsUiTCdi iSymbolParameterMinTypMaxUnitTest ConditionsVIHI nput HIGH Input HIGH Voltage forAll InputsVILI nput LOW Input LOW Voltage forVILI nput LOW InputsVIKI nput Clamp Diode Voltage = MIN, IIN = 18 mAVOHO utput HIGH = MIN, IOH = MAX, VIN = VIHVOHO utput HIGH ,OH,INIHor VIL per Truth TableVOLO utput LOW Voltage54, = mAVCC = VCC MIN,VIN=VILor VIHVOLO utput LOW = mAVIN = VIL or VIHper Truth TableIIHI nput HIGH Current20 AVCC = MAX, VIN = VIIHI nput HIGH = MAX, VIN = VIILI nput LOW Current = MAX, VIN = VIOSS hort Circuit Current (Note 1) 20 100mAVCC = MAXICCP ower Supply Current34mAVCC = MAXNote 1.

10 Not more than one output should be shorted at a time, nor for more than 1 CHARACTERISTICS (TA = 25 C)SblPLimitsUiTCdi iSymbolParameterMinTypMaxUnitTest ConditionsfMAXM aximum Clock Frequency2532 MHzV50 VtPLHtPHLCPU Input toTCU Output17182624nsV50 VtPLHtPHLCPD Input toTCD Output16152424nsVCC = VtPLHtPHLC lock to Q27303847nsCCCL = 15 pFtPLHtPHLPL to Q24254040nstPHLMR Input to Any Output2335ns5-6 FAST AND LS TTL DATASN54/ 74ls192 sn54 /74LS193AC SETUP REQUIREMENTS (TA = 25 C)SblPLimitsUiTCdi iSymbolParameterMinTypMaxUnitTest ConditionstWAny Pulse Width20nsV50 VtsData Setup Time20nsVCC=50 VthData Hold = VtrecRecovery Time40nsDEFINITIONS OF TERMSSETUP TIME (ts) is defined as the minimum time required forthe correct logic level to be present at the logic input prior to thePL transition from LOW-to-HIGH in order to be recognized andtransferred to the TIME (th) is defined as the minimum time following thePL transition from LOW-to-HIGH that the logic level must bemaintained at the input in order to ensure continued recogni-tion.