Spartan-6 FPGA Configurable Logic Block

1 Spartan-6 FPGA Configurable Logic BlockUser GuideUG384 ( ) February 23, 2010 Spartan-6 FPGA CLB User ( ) February 23, 2010 xilinx is disclosing this user guide, manual , release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of xilinx . xilinx expressly disclaims any liability arising out of your use of the Documentation. xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time.

2 xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. xilinx MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL xilinx BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

3 2009 2010 xilinx , Inc. xilinx , the xilinx logo, Virtex, spartan , ISE, and other designated brands included herein are trademarks of xilinx in the United States and other countries. All other trademarks are the property of their respective HistoryThe following table shows the revision history for this document. DateVersionRevision06/24 xilinx the Slice Description section. Added Figure 6. Clarifying edits to Storage Elements, Initialization, Distributed RAM and Memory (SLICEM only), and Fast Lookahead Carry Logic sections. Added Using the Latch Function as Logic and Interconnect Resources. Updated parameter names in Ta b l e 9 and Ta b l e 1 0 and Figure 35. Updated description TCINA function and description Ta b l e 1 FPGA CLB User ( ) February 23, 2010 Revision History.

4 2 Preface: About This GuideAdditional Documentation.. 5 Additional Support Resources.. 6 Spartan-6 FPGA CLBCLB Overview .. 7 Slice Description.. 8 CLB/Slice Configurations .. 12 Look-Up Table (LUT) .. 12 Storage Elements .. 13 Distributed RAM and Memory (SLICEM only) .. 15 Read Only Memory (ROM) .. 25 Shift Registers (SLICEM only) .. 25 Multiplexers .. 30 Designing Large Multiplexers .. 31 Fast Lookahead Carry Logic .. 33 Using the Latch Function as Logic .. 35 Interconnect Resources.. 36 Spartan-6 FPGA Interconnect Types .. 36 Global Controls .. 39 STARTUP_SPARTAN6 Primitive .. 39 Interconnect Summary .. 39 CLB / Slice Timing Models.. 41 Slice (LUT and Storage Element) Timing Models.

5 41 Slice Distributed RAM Timing Model (SLICEM only) .. 45 Slice SRL Timing Model (SLICEM only) .. 48 Slice Carry-Chain Timing Model (SLICEM and SLICEL only) .. 50 CLB Primitives.. 52 Distributed RAM Primitives .. 52 Shift Registers (SRLs) Primitive .. 54 Other Shift Register Applications .. 55 Multiplexer Primitives .. 56 Carry Chain Primitive .. 57 Table of FPGA CLB User GuideUG384 ( ) February 23, 2010 Spartan-6 FPGA CLB User ( ) February 23, 2010 PrefaceAbout This GuideThis guide serves as a technical reference describing the spartan -6 FPGA Configurable Logic blocks (CLBs). Usually, the Logic synthesis software assigns the CLB resources without system designer intervention. It can be advantageous for the designer to understand certain CLB details, including the varying capabilities of the look-up tables (LUTs), the physical direction of the carry propagation, the number and distribution of the available flip-flops, and the availability of the very efficient shift registers.

6 This guide describes these and other features of the CLB in DocumentationThe following documents are also available for download at Spartan-6 Family OverviewThis overview outlines the features and product selection of the Spartan-6 family. Spartan-6 FPGA Data Sheet: DC and Switching CharacteristicsThis data sheet contains the DC and switching characteristic specifications for the Spartan-6 family. Spartan-6 FPGA Packaging and Pinout SpecificationsThis specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications. Spartan-6 FPGA Configuration User GuideThis all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

7 Spartan-6 FPGA SelectIO Resources User GuideThis guide describes the SelectIO resources available in all Spartan-6 devices. Spartan-6 FPGA Clocking Resources User GuideThis guide describes the clocking resources available in all Spartan-6 devices, including the DCMs and PLLs. Spartan-6 FPGA Block RAM Resources User GuideThis guide describes the Spartan-6 device Block RAM capabilities. Spartan-6 FPGA GTP Transceivers User GuideThis guide describes the GTP transceivers available in the Spartan-6 LXT FPGA CLB User GuideUG384 ( ) February 23, 2010 Preface:About This Guide Spartan-6 FPGA DSP48A1 Slice User GuideThis guide describes the architecture of the DSP48A1 slice in Spartan-6 fpgas and provides configuration examples.

8 Spartan-6 FPGA Memory Controller User GuideThis guide describes the Spartan-6 FPGA memory controller Block , a dedicated embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 fpgas to the most popular memory standards. Spartan-6 FPGA PCB Design GuideThis guide provides information on PCB design for Spartan-6 devices, with a focus on strategies for making design decisions at the PCB and interface Support ResourcesTo search the database of silicon and software questions and answers or to create a technical support case in WebCase, see the xilinx website at: FPGA CLB User ( ) February 23, 2010 Spartan-6 FPGA CLBCLB OverviewThe Configurable Logic Blocks (CLBs) are the main Logic resources for implementing sequential as well as combinatorial circuits.

9 Each CLB element is connected to a switch matrix for access to the general routing matrix (shown in Figure 1). A CLB element contains a pair of slices. These two slices do not have direct connections to each other, and each slice is organized as a column. For each CLB, the slice in the bottom of the CLB is labeled as SLICE(0), and the slice in the top of the CLB is labeled as SLICE(1).The xilinx tools designate slices with the following definitions. An X followed by a number identifies the position of each slice in a pair as well as the column position of the slice. The X number counts slices starting from the bottom in sequence 0, 1 (the first CLB column); 2, 3 (the second CLB column); etc. A Y followed by a number identifies a row of slices.

10 The number remains the same within a CLB, but counts up in sequence from one CLB row to the next CLB row, starting from the bottom. Figure 2 shows four CLBs located in the bottom-left corner of the Target - Figure 1 Figure 1:Arrangement of Slices within the CLBS witchMatrixSlice(1)COUTCINS lice(0) FPGA CLB User GuideUG384 ( ) February 23, 2010 Slice DescriptionEvery slice contains four Logic -function generators (or look-up tables, LUTs) and eight storage elements. These elements are used by all slices to provide Logic and ROM functions (Ta b l e 1). SLICEX is the basic slice. Some slices, called SLICELs, also contain an arithmetic carry structure that can be concatenated vertically up through the slice column, and wide-function multiplexers.