C8051F34x Full Speed USB Flash MCU Family Data Sheet

1 C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/DRev. 10/22 Copyright 2022 by Silicon LaboratoriesC8051F34xFull Speed USB Flash MCU FamilyAnalog Peripherals-10-Bit ADC (C8051F340/1/2/3/4/5/6/7/A/B only) Up to 200 ksps Built-in analog multiplexer with single -ended and differential mode VREF from external pin, internal reference, or VDD Built-in temperature sensor External conversion start input option-Two comparators-Internal voltage reference (C8051F340/1/2/3/4/5/6/7/A/B only)-Brown-out detector and POR CircuitryUSB Function Controller-USB specification compliant-Full Speed (12 Mbps) or low Speed ( Mbps) operation-Integrated clock recovery; no external crystal required for full Speed or low Speed -Supports eight flexible endpoints-1 kB USB buffer memory-Integrated transceiver; no external resistors requiredOn-Chip Debug-On-chip debug circuitry facilitates full Speed , non-intru-sive in-system debug (No emulator required)-Provides breakpoints, single stepping, inspect/modify memory and registers-Superior performance to emulation systems using ICE-chips, target pods, and socketsVoltage supply Input: to V-Voltages from to V supported using On-Chip Voltage RegulatorHIgh Speed 8051 C Core-Pipelined instruction architecture; executes 70% of Instructions in 1 or 2 system clocks-48 MIPS and 25 MIPS versions interrupt handlerMemory-4352 or 2304 Bytes RAM-64 or 32 kB Flash ; In-system programmable in 512-byte sectorsDigital Peripherals-40/25 Port I/O.

2 All 5 V tolerant with high sink current-Hardware enhanced SPI , SMBus , and one or two enhanced UART serial ports-Four general purpose 16-bit counter/timers-16-bit programmable counter array (PCA) with five cap-ture/compare modules-External Memory Interface (EMIF)Clock Sources-Internal Oscillator: accuracy with clock recovery enabled. Supports all USB and UART modes-External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin modes)-Low Frequency (80 kHz) Internal Oscillator-Can switch between clock sources on-the-flyPackages-48-pin TQFP (C8051F340/1/4/5/8/C)-32-pin LQFP (C8051F342/3/6/7/9/A/B/D)-5x5 mm 32-pin QFN (C8051F342/3/6/7/9/A/B)Temperature Range: 40 to +85 CC8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 2 Rev. Rev. of Contents1. System 172. Absolute Maximum Ratings .. 253. Global DC Electrical Characteristics .. 264. Pinout and Package 295.

3 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only).. Analog Multiplexer .. Temperature Modes of Operation .. Starting a Tracking Settling Time Programmable Window Window Detector In single -Ended Mode .. Window Detector In Differential 566. Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only).. 587. Comparators .. 608. Voltage Regulator (REG0).. Regulator Mode VBUS 709. CIP-51 Microcontroller .. Instruction Instruction and CPU Timing .. MOVX Instruction and Program Memory .. Memory Program data General Purpose Bit Addressable Stack .. Special Function Register Descriptions .. Interrupt MCU Interrupt Sources and Vectors .. External Interrupt Interrupt Latency .. Interrupt Register Power Management Idle Stop Engine .. 102C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 4 Rev.

4 Reset / VDD Monitor .. Clock Detector Reset .. Reset .. Watchdog Timer Reset .. Error Reset .. Memory .. The Flash Lock and Key Erase Procedure .. Write Procedure .. data Options .. data Memory Interface and On-Chip MOVX Example .. MOVX Example .. USB FIFO Space .. the External Memory and Non-multiplexed Mode XRAM Only .. Mode without Bank Mode with Bank .. Mode .. Internal High-Frequency (H-F) H-F Oscillator Suspend Internal Low-Frequency (L-F) Oscillator .. the Internal L-F Oscillator Drive Timers Directly Through the External Crystal RC Capacitor Clock Multiplier .. and USB Clock Selection .. 140C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Rev. Clock Selection .. Clock Crossbar Decoder.

5 I/O Initialization .. Purpose Port Serial Bus Controller (USB0).. Addressing .. Transceiver .. Register Access .. Clock Management .. Split Double Buffering .. Access .. Configuration and .. Serial Interface .. SETUP Transactions .. IN OUT Endpoints1-3 IN Interrupt or Bulk IN Isochronous Endpoints1-3 OUT Interrupt or Bulk OUT Isochronous .. Low Low High (SMBus Free) Timeout .. the Configuration Control Register .. Register .. Transfer Transmitter Receiver 201C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 6 Rev. Receiver Transmitter Status Baud Rate Communications .. (C8051F340/1/4/5/8/A/B/C Only).. Rate Generator .. and Operation .. Transmission .. Reception.

6 Serial Peripheral Interface (SPI0).. Out, Slave In (MOSI).. In, Slave Out (MISO).. Clock (SCK) .. Select (NSS) .. Master Mode Slave Mode Interrupt Sources .. Clock Special Function 0 and Timer 1 .. 0: 13-bit Counter/Timer .. 1: 16-bit Counter/Timer .. 2: 8-bit Counter/Timer with 3: Two 8-bit Counter/Timers (Timer 0 Only).. 2 .. Timer with Timers with 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge .. 3 .. Timer with Timers with Start-of-Frame Counter Array (PCA0) .. Counter/Timer .. Modules .. Capture 259C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Rev. Timer (Compare) Speed Output Output Mode .. Pulse Width Modulator Pulse Width Modulator Timer Mode .. Timer Timer Usage .. Descriptions for Interface Pin Sharing.

7 274 Document Change 275 Contact 277C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D 8 Rev. of Figures1. System OverviewFigure C8051F340/1/4/5 Block Diagram .. 20 Figure C8051F342/3/6/7 Block Diagram .. 21 Figure C8051F348/C Block 22 Figure C8051F349/D Block 23 Figure C8051F34A/B Block Diagram .. 242. Absolute Maximum Ratings3. Global DC Electrical Characteristics4. Pinout and Package DefinitionsFigure TQFP-48 Pinout Diagram (Top View) .. 32 Figure TQFP-48 Package 33 Figure TQFP-48 Recommended PCB Land Pattern .. 34 Figure LQFP-32 Pinout Diagram (Top View).. 35 Figure LQFP-32 Package Diagram .. 36 Figure LQFP-32 Recommended PCB Land Pattern .. 37 Figure QFN-32 Pinout Diagram (Top View) .. 385. 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)Figure ADC0 Functional Block 42 Figure Temperature Sensor Transfer Function.

8 44 Figure Temperature Sensor Error with 1-Point Calibration (VREF = V).. 45 Figure 10-Bit ADC Track and Conversion Example Timing .. 47 Figure ADC0 Equivalent Input 48 Figure ADC Window Compare Example: Right-Justified single -Ended data .. 55 Figure ADC Window Compare Example: Left-Justified single -Ended 55 Figure ADC Window Compare Example: Right-Justified Differential 56 Figure ADC Window Compare Example: Left-Justified Differential 566. Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only)Figure Voltage Reference Functional Block 587. ComparatorsFigure Comparator Functional Block Diagram .. 61 Figure Comparator Hysteresis Plot .. 628. Voltage Regulator (REG0)Figure REG0 Configuration: USB Bus-Powered .. 71 Figure REG0 Configuration: USB Self-Powered .. 71 Figure REG0 Configuration: USB Self-Powered, Regulator 72 Figure REG0 Configuration: No USB 729.

9 CIP-51 MicrocontrollerFigure CIP-51 Block 74 Figure On-Chip Memory Map for 64 kB 80 Figure On-Chip Memory Map for 32 kB 8110. Prefetch EngineC8051F340/1/2/3/4/5/6/7/8/9/A/B/C/ D Rev. Reset SourcesFigure Reset 101 Figure Power-On and VDD Monitor Reset Timing .. 10212. Flash MemoryFigure Flash Program Memory Map and Security 11113. External data Memory Interface and On-Chip XRAMF igure USB FIFO Space and XRAM Memory Map with USBFAE set to 1 .. 116 Figure Multiplexed Configuration 120 Figure Non-multiplexed Configuration 121 Figure EMIF Operating Modes .. 121 Figure Non-multiplexed 16-bit MOVX 125 Figure Non-multiplexed 8-bit MOVX without Bank Select Timing .. 126 Figure Non-multiplexed 8-bit MOVX with Bank Select Timing .. 127 Figure Multiplexed 16-bit MOVX 128 Figure Multiplexed 8-bit MOVX without Bank Select Timing.

10 129 Figure Multiplexed 8-bit MOVX with Bank Select Timing .. 13014. OscillatorsFigure Oscillator 13215. Port Input/OutputFigure Port I/O Functional Block Diagram (Port 0 through Port 3) .. 143 Figure Port I/O Cell Block Diagram .. 144 Figure Peripheral Availability on Port I/O 145 Figure Crossbar Priority Decoder in Example Configuration (No Pins Skipped) .. 146 Figure Crossbar Priority Decoder in Example Configuration (3 Pins Skipped) ..14716. Universal Serial Bus Controller (USB0)Figure USB0 Block 160 Figure USB0 Register Access 163 Figure USB FIFO Allocation .. 16817. SMBusFigure SMBus Block Diagram .. 189 Figure Typical SMBus 190 Figure SMBus 191 Figure Typical SMBus SCL 194 Figure Typical Master Transmitter 200 Figure Typical Master Receiver 201 Figure Typical Slave Receiver 202 Figure Typical Slave Transmitter 20318.