Axi Uart
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AXI UART Lite v2 - Xilinx
www.xilinx.comThe AXI UART Lite resource ut ilization for various parameter co mbinations measured with a 7 series device. Note: Resource numbers for UltraScale architecture-based devices and Zynq devices are expected to be similar to 7 series device numbers. Port Descriptions The AXI UART Lite I/O signals are listed and described in Table 2-3.
i.MX 6Solo/6DualLite Applications Processors Data Sheet ...
www.nxp.comand a variety of other popular interfaces (such as UART, I2C, and I2S serial audio, and PCIe-II). † Advanced security—The processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, secure boot, and secure software downloads.
Hardware and Software Requirements - Xilinx
www.xilinx.com1. All axi_ethernet-based systems are built with full checksum (both TCP and IP checksums) offload feature. 2. The axi_ethernetlite-based systems are built with ping-pong buffers (one more buffer for both TX and RX paths to improve performance). 3. The GigE-based systems (Zynq-7000 AP SoC devices) have a built-in TCP/IP checksum offload support.