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Chapter 4 Calculating the Logical Effort of Gates

NAND gate is LOW, the output must be pulled HIGH, and so the output drive of the NAND gate must match that of the inverter even if only one of the two pullups is conducting. We find the logical effort of the NAND gate in Figure 4.1b by extracting ca-pacitances from the circuit schematic. The input capacitance of one input signal

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