Search results with tag "Channel counter"

S32K1xx Series Cookbook - NXP

Summary: This project provides common in itialization for clocks and an LPIT channel counter function. Core clock is set to 80 MHz. LPIT0 channel 0 is configured to count one second of SPLL clocks. Software polls the channel’s timeout flag and toggles the GPIO output to the LED when the flag sets. Figure 2. Hello World + Clocks block diagram PTD0

  Channel, Counter, Channel counter