Search results with tag "Cadence tutorial b"

Cadence Tutorial B: Layout, DRC, Extraction, and LVS

layout should contain the same pin names and the transistors must be made the same size as those in the schematic. In this tutorial the nMOS and pMOS transistors both use the minimum size transistor dimensions (W = 1.5um and L = 0.6um) for the AMI C5N process.

  Tutorials, Layout, Extraction, Cadence, Cadence tutorial b, And lvs