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Evaluating the HMC7044 Dual Loop Clock Jitter Cleaner
www.analog.comradio card clock tree designs. The high performance dual-loop core of the HMC7044 enables the base station designer to attenuate the incoming jitter of a primary system reference clock, such as a CPRI source, with the help of the narrow-band configured first PLL loop, which disciplines an external VCXO, and to generate