Search results with tag "Macrocell"
DESIGNWARE DW8051 MACROCELL SOLUTION
www.keil.comOVERVIEW The DesignWare® DW8051™ MacroCell is a high-performance, configurable, fully-synthesizable, and reusable 8051 core. It is fully binary compatible with the industry standard 803x/805x microcontrollers. An encrypted version of the DW8051 MacroCell is available to all DesignWare Foundation Library users
0 R XC9572XL High Performance CPLD - Xilinx
www.xilinx.comloading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addi-tion, unused product-terms and macrocells are automati-cally deactivated by the software to further conserve power. For a general estimate of I CC, the following equation may be used:
R XC2C64A CoolRunner-II CPLD - Xilinx
www.xilinx.comThe CoolRunner-II 64-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand …
ARM® Cortex®-M4 32b MCU+FPU, 105 DMIPS, 512KB …
www.st.com–Cortex®-M4 Embedded Trace Macrocell™ • Up to 81 I/O ports with interrupt capability – Up to 78 fast I/Os up to 42 MHz – All I/O ports are 5 V-tolerant • Up to 12 communication interfaces – Up to 3 x I2C interfaces (SMBus/PMBus) – Up to 3 USARTs (2 x 10.5 Mbit/s, 1 x 5.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control)
Arm® Cortex®-M4 32b MCU+FPU, 105 DMIPS, 256KB …
www.st.com–Cortex®-M4 Embedded Trace Macrocell™ • Up to 81 I/O ports with interrupt capability – All IO ports 5 V tolerant – Up to 78 fast I/Os up to 42 MHz • Up to 11 communication interfaces – Up to 3 × I2C interfaces (1Mbit/s, SMBus/PMBus) – Up to 3 USARTs (2 x 10.5 Mbit/s, 1 x 5.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control)
S32K1XX: S32K1xx Data Sheet
www.nxp.com.cn– Instrumentation Trace Macrocell (ITM) – Test Port Interface Unit (TPIU) – Flash Patch and Breakpoint (FPB) Unit • Human-machine interface (HMI) – Up to 156 GPIO pins with interrupt functionality – Non-Maskable Interrupt (NMI) NXP Semiconductors Document Number S32K1XX Data Sheet: Technical Data Rev. 14, 08/2021
USB3300 Data Sheet
ww1.microchip.com• USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000 • UTMI+ Specification, Revision 1.0, February 2, 2004 • UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1 FIGURE 1-2: ULPI INTERFACE FEATURES AS RELATED TO UTMI+ UTMI+ Level 0 Hi-Speed Peripherals Only ADDED FEATURES USB3300 ULPI
AN958: Debugging and Programming Interfaces for Custom …
www.silabs.com• ETM* (embedded trace macrocell) • Debug component which enables reconstruction of program execution, and is designed as a high-speed, low-power debug tool that only supports instruction trace. • AEM (advanced energy monitoring)