0 XC9572 In-System Programmable CPLD

1 DS065 ( ) May 17, Specification 1998, 2003 2006, 2013 xilinx , Inc. All rights reserved. All xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. PRODUCT OBSOLETE / UNDER OBSOLESCENCE Features ns pin-to-pin logic delays on all pins fCNT to 125 MHz 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V In-System Programmable -Endurance of 10,000 program/erase cycles-Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block-90 product terms drive any or all of 18 macrocells within Function Block-Global and product term clocks, output enables, set and reset signals Extensive IEEE Std boundary-scan (JTAG)

2 Support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User Programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs or 5V I/O capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP packagesDescriptionThe XC9572 is a high-performance CPLD providingadvanced In-System programming and test capabilities forgeneral purpose logic integration. It is comprised of eight36V18 Function Blocks, providing 1,600 usable gates withpropagation delays of ns.

3 See Figure 2 for the architec-ture ManagementPower dissipation can be reduced in the XC9572 by config-uring macrocells to standard or low-power modes of opera-tion. Unused macrocells are turned off to minimize current for each design can be approximated forspecific operating conditions using the following equation:ICC (mA) = MCHP ( ) + MCLP ( ) + MC ( mA/MHz) fWhere:MCHP = Macrocells in high-performance modeMCLP = Macrocells in low-power modeMC = Total number of macrocells usedf = Clock frequency (MHz)Figure 1 shows a typical calculation for the XC9572 In-System Programmable CPLDDS065 ( ) May 17, 201305 Product SpecificationRFigure 1: Typical ICC vs.

4 Frequency for XC9572 Clock Frequency (MHz)Typical ICC (mA)050100(65)(125)(160)(100)200100 High PerformanceLow PowerDS065_01_110501XC9572 In-System Programmable ( ) May 17, 2013 Product SpecificationR PRODUCT OBSOLETE / UNDER OBSOLESCENCE Figure 2: XC9572 ArchitectureFunction block outputs (indicated by the bold line) drive the I/O blocks Programming ControllerJTAGC ontrollerI/OBlocksFunctionBlock 1 Macrocells1 to 18 Macrocells1 to 18 JTAG Port336I/O/GTSI/O/GSRI/O/GCKI/OI/OI/OI/O 21I/OI/OI/OI/O3DS065_02_1101011 FunctionBlock 2361818 FunctionBlock 3 Macrocells1 to 183618 FunctionBlock 4 Macrocells1 to 183618 Fast CONNECT II Switch MatrixXC9572 In-System Programmable CPLDDS065 ( )

5 May 17, SpecificationR PRODUCT OBSOLETE / UNDER OBSOLESCENCE Absolute Maximum RatingsRecommended Operation ConditionsQuality and Reliability CharacteristicsDC Characteristic Over Recommended Operating ConditionsSymbolDescriptionValueUnitsVCC S upply voltage relative to GND to voltage relative to GND to VCC + applied to 3-state output to VCC + temperature (ambient) 65 to +150oCTJJ unction temperature+150oCNotes: beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.

6 Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device voltage for internal logic and input buffersCommercial TA = 0oC to TA = 40oC to + voltage for output drivers for 5V operationCommercial TA = 0oC to TA = 40oC to + voltage for output drivers for input input + voltage0 VCCIOVS ymbolParameterMinMaxUnitsTDRData Retention20-YearsNPEP rogram/Erase Cycles (Endurance)10,000-CyclesSymbolParameterT est ConditionsMinMaxUnitsVOHO utput high voltage for 5V outputsIOH = mA, VCC = high voltage for outputsIOH = mA, VCC = low voltage for 5V outputsIOL = 24 mA, VCC = low voltage for outputsIOL = 10 mA, VCC = leakage currentVCC = MaxVIN = GND or VCC- 10 AIIHI/O high-Z leakage currentVCC = MaxVIN = GND or VCC- 10 ACINI/O capacitanceVIN = GNDf = MHz-10pFICCO perating supply current(low power mode, active)VI = GND, No loadf = MHz65 (Typical)mAXC9572 In-System Programmable ( )

7 May 17, 2013 Product SpecificationR PRODUCT OBSOLETE / UNDER OBSOLESCENCE AC CharacteristicsSymbolParameterXC9572-7XC 9572-10XC9572-15 UnitsMinMaxMinMaxMinMaxTPDI/O to output setup time before hold time after GCK0-0-0-nsTCOGCK to output (1)16-bit counter (2)Multiple FB internal operating setup time before p-term clock hold time after p-term clock clock output to output to output term OE to output term OE to output pulse width (High or Low) preset/reset pulse width (High or Low) : is the fastest 16-bit counter frequency available, using the local feedback when applicable. fCNT is also the Export Control Maximum flip-flop toggle rate, is the internal operating frequency for general purpose system designs spanning multiple 3.

8 AC Load CircuitDevice OutputOutput 260 R1R2 CLR2 120 360 CL35 pF35 In-System Programmable CPLDDS065 ( ) May 17, SpecificationR PRODUCT OBSOLETE / UNDER OBSOLESCENCE Internal Timing ParametersSymbolParameterXC9572-7XC9572- 10XC9572-15 UnitsMinMaxMinMaxMinMaxBuffer DelaysTINI nput buffer buffer buffer buffer buffer buffer enable/disable delay-0-0-0nsProduct Term Control DelaysTPTCKP roduct term clock term set/reset term 3-state Register and Combinatorial DelaysTPDIC ombinatorial logic propagation setup hold clock to output valid async. S/R to output async. S/R recover before logic low power logic DelaysTFFastCONNECT feedback block local feedback AddersTPTA(1)Incremental product term allocator limited.

9 Is multiplied by the span of the function as defined in the XC9500 family data In-System Programmable ( ) May 17, 2013 Product SpecificationR PRODUCT OBSOLETE / UNDER OBSOLESCENCE XC9572 I/O PinsFunction BlockMacro-cellPC44PC84PQ100TQ100 BScan OrderFunction BlockMacro-cellPC44PC84PQ100TQ100 BScan Order11 4181621331 25434110512111513210321117343210213 6201820733 3151499914 7222020434 3252509615221614201351219373593163317151 9836 3455539017 11272519537 3556548718451917192381321393784195[1]9[1 ]24[1]22[1]189391426444281110 133028186310 406260781116[1]10[1]25[1]23[1]1833111833 545275112 183533180312 41636172113 203836177313 436563691147[1]12[1]29[1]27[1]

10 1743141936575566115814312917131520375856 63116 234139168316 4567656011791532301653172239605857118 244240162318 61595421 63898715941 46686651223569969415642244466644823 67939115343 5173714524 68959315044 5274724225367097951474525476967392637719 89614446 5478763627 76[2]5[2]3[2]14147 5579773328387299971384826487068302939[1] 74[1]1[1]99[1]135492750727027210 7531132410 5783812421140[1]77[1]6[1]4[1]12941128537 67421212 7986126412 58848218213 80108123413 6187851521442[3]81[3]11[3]9[3]1204142956 80781221543831311117415336591899216 821210114416 628886621744841412111417346692903218 9492108418 81790 Notes: control control pin GTS1 for PC84, PQ100, and control pin GTS1 for In-System Programmable CPLDDS065 ( )