1章ディジタル回路の基礎

1 2006/10/03 2006, Masaharu Imai1 1 E-mail: 2006, Masaharu Imai2 MOS FET CMOS 2006/10/03 2006, Masaharu Imai3 2006/10/03 2006, Masaharu Imai4 2006/10/03 2006, Masaharu Imai5 x= (t) x, t (t) n 2006/10/03 2006, Masaharu Imai6 0501001502002503000123456789 2006, Masaharu Imai7 2006/10/03 2006, Masaharu Imai8 1812111231532501805020118015905010015020 025030012345678910 2006/10/03 2006, Masaharu Imai9 011 2 3 4 5 6 7 8 9 10111213141516 1 1 0 1 0 0 1 11 0 1 1 0 1 0 11812112006/10/03 2006, Masaharu Imai10 Threshold Level HLVTHVTL2006/10/03 2006, Masaharu Imai11 VTHVTL2006/10/03 2006, Masaharu Imai12 MOS FET CMOS 2006/10/03 2006, Masaharu Imai13 MOS FET MOS = Metal O side Semiconductor FET = Field Effect Transistor nMOS FET 5 Electron pMOS FET Positive Hole nMOS pMOS 2006/10/03 2006, Masaharu Imai14nMOS FET )N+N+GDSPS: Source G: Gate D.

2 Drain2006/10/03 2006, Masaharu Imai15nMOS FET (1) VG=VS N+N+GDSPS: SourceG: GateD: Drain2006/10/03 2006, Masaharu Imai16nMOS FET (2) VG VS + VTH N VTH N+N+GDSPS: SourceG: GateD: DrainN Channel2006/10/03 2006, Masaharu Imai17 MOS FET VGS-VGSVTHVTH ID-IDnMOSpMOS2006/10/03 2006, Masaharu Imai18nMOS FET ( ) VSG=0V ISD>0 GDSPN+N+N-S: SourceG: GateD: Drain2006/10/03 2006, Masaharu Imai19 MOS FET VGS-VGSVTHVTH ID-IDnMOSpMOS2006/10/03 2006, Masaharu Imai20n MOS VCCGNDEnMOSVCCGNDEnMOSVCCGNDDnMOSEnMOSEn MOSRLE/E nMOSE/D nMOS2006/10/03 2006, Masaharu Imai21 MOS FET CMOS 2006/10/03 2006, Masaharu Imai22 CMOS FET N+N+GSDP-wellP+GDSP-SubstratenMOS FETpMOS FETP+N-well2006/10/03 2006, Masaharu Imai23 CMOS=Complementary MOS pMOS Tr nMOSTr ON OFFpMOSTr nMOSTr.

3 VCCGND ..2006/10/03 2006, Masaharu Imai24 NOT A YVCCGNDPN HLLH2006/10/03 2006, Masaharu Imai25 A H A L A=H Y=LVCCGNDOFFON A=L Y=HVCCGNDONOFF2006/10/03 2006, Masaharu Imai26 NAND YVCCGND A B A B YLLHLHHHLHHHL2006/10/03 2006, Masaharu Imai27 NOR YVCCGND A B A B YLLHLHLHLLHHL2006/10/03 2006, Masaharu Imai28 - - VOHVOLVDSVTHVTLVGSpMOSnMOS2006/10/03 2006, Masaharu Imai29 GNDVCCVOHVOLVTLVTH 2006/10/03 2006, Masaharu Imai30 MOS FET CMOS 2006/10/03 2006, Masaharu Imai31 Threshold Level HLVTHVTL2006/10/03 2006, Masaharu Imai32 HVTHLHLVTL2006/10/03 2006, Masaharu Imai33 HVTH+LVTL-HL2006/10/03 2006, Masaharu Imai34 HL VTH VTH-2006/10/03 2006, Masaharu Imai35 Vcc2006/10/03 2006, Masaharu Imai36 MOS FET CMOS 2006/10/03 2006, Masaharu Imai37 H , L 3 Z Tri-State ( Z ) 2006/10/03 2006, Masaharu Imai38 D_inD_outC_in2C_in1C_in2D_inD_out 0 1 0 Z 0 1 1 Z 1 0 0 0 1 0 1 1 D_inD_outC_in12006/10/03 2006, Masaharu Imai39 D_in1D_in2D_in3D_in4 0 0 1 0 D_in1 Z Z Z 2006/10/03 2006, Masaharu Imai40 2006/10/03 2006, Masaharu Imai41 (1) MOS NMOS PMOS 2 CMOS NMOS PMOS CMOS NMOS PMOS 2006/10/03 2006, Masaharu Imai42 (2)

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