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第10章シリアル通信制御回路

2007/01/16 2007, Masaharu Imai1 10 E-mail: 2007, Masaharu Imai2 RS232C Dsub 9 VHDL 2007/01/16 2007, Masaharu Imai3RS232C (DTE) (DCE) DTE: Data Terminal Equipment DCE: Data Circuit Equipment DTE DCE DTE DCE RS232 CRS232C2007/01/16 2007, Masaharu Imai4RS232C DTE DCE RS232C DTE DTE RS232C I/O DCE DTE 2007/01/16 2007, Masaharu Imai5 DTR (DTE)DSR (DCE)RTS (DTE)CTS (DCE)DCD (DCE) TxD (DTE)RxD (DCE)2007/01/16 2007, Masaharu Imai6 DTE DCE ON ON 3.

2007/01/16 ©2007, Masaharu Imai 1 第10章シリアル通信制御回路 大阪大学大学院情報科学研究科 今井正治 E-mail: imai@ist.osaka-u.ac.jp

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Transcription of 第10章シリアル通信制御回路

1 2007/01/16 2007, Masaharu Imai1 10 E-mail: 2007, Masaharu Imai2 RS232C Dsub 9 VHDL 2007/01/16 2007, Masaharu Imai3RS232C (DTE) (DCE) DTE: Data Terminal Equipment DCE: Data Circuit Equipment DTE DCE DTE DCE RS232 CRS232C2007/01/16 2007, Masaharu Imai4RS232C DTE DCE RS232C DTE DTE RS232C I/O DCE DTE 2007/01/16 2007, Masaharu Imai5 DTR (DTE)DSR (DCE)RTS (DTE)CTS (DCE)DCD (DCE) TxD (DTE)RxD (DCE)2007/01/16 2007, Masaharu Imai6 DTE DCE ON ON 3.

2 OFF OFF ON 3. OFF 2007/01/16 2007, Masaharu Imai7 DTE DCE ON ON 3. OFF OFF ON 3. OFF 2007/01/16 2007, Masaharu Imai8 DCE DTE ON 2. OFF ON 2. OFF 2007/01/16 2007, Masaharu Imai9 JIS FGSDRDRSCSDRGNDSG ((Signal) Ground)CDERCITxD (Frame Ground) DTR RIRxDRTSCTSDSR DCD2007/01/16 2007, Masaharu Imai10RS232C LH -25 -3 V+3 +25 V 1 0 2007/01/16 2007, Masaharu Imai11 00110001D7D6D5D4D3D2D1D0 D7D6D5D4D3D2D1D0 00110001 (H) (L)

3 2007/01/16 2007, Masaharu Imai12 bps, baud 300, 600, 1200, 2400, 4800, 9600, , , , 7 bit 8 bit 1 bit 1 bit, bit 2 bit2007/01/16 2007, Masaharu Imai13 RS232C Dsub 9 VHDL 2007/01/16 2007, Masaharu Imai149 Dsub 9 Dsub 123456789 1CD 2RD3TD (SD)4 DTR5 GND6 DSR7 RTS8 CTS9RI2007/01/16 2007, Masaharu Imai15 DTE DCE DTE TDRDRTSCTSCDDTRDSRRIGND327814695 DCE TDRDRTSCTSCDDTRDSRRIGND3278146952007/01/ 16 2007, Masaharu Imai16 DTE DTE / DTE TDRDRTSCTSCDDTRDSRRIGND327814695 DTE TDRDRTSCTSCDDTRDSRRIGND327814695(OPEN)20 07/01/16 2007, Masaharu Imai17 RS232C Dsub 9 VHDL 2007/01/16 2007, Masaharu Imai18 1 0110001 (31H) 1 0110001 (B1H) 0110001 (31H) 0 0110001 (31H)

4 RS232C 7 2007/01/16 2007, Masaharu Imai19 d[0]d[1]d[2]d[3]d[4]d[5]d[6]o_ebeboddddd ddp_]6[]5[]4[]3[]2[]1[]0[ =2007/01/16 2007, Masaharu Imai20 d[0]d[1]d[2]d[3]d[4]d[5]d[6]d[7]]7[]6[]5 []4[]3[]2[]1[]0[_ddddddddebo =2007/01/16 2007, Masaharu Imai21 RS232C Dsub 9 VHDL 2007/01/16 2007, Masaharu Imai22 00110001D7D6D5D4D3D2D1D0 D7D6D5D4D3D2D1D0 00110001 (H) (L) 2007/01/16 2007, Masaharu Imai23 DTE H H 3. 4. LSB 5. 5 L L 9. 2007/01/16 2007, Masaharu Imai24 DCE 1.

5 RTS H CTS H 2. 3. LSB 4. 4 L CTS L 7. 2007/01/16 2007, Masaharu Imai25 STAD0D1D2D3D4D5D6D7 STO T/16T/2 TTTTTTTTTTT, , 2TT/22007/01/16 2007, Masaharu Imai26 7 8 2007/01/16 2007, Masaharu Imai27 start = 1 start = 0 & done_s = 1 done_s = 0 done_s = 1 IDLE:sent <= 1 SEND_0:sent <= 0 SEND_1:start_s <= 1 SEND_2:start_s <= 0 2007/01/16 2007, Masaharu Imai28 IDLE:done <= 1 rts <= 0 txd <= STOP_BITSEND_RDY:done <= 0 rts <= 1 SEND_START_B:txd <= START_BITbit_pos.

6 = 0 SEND_DATA:txd <= d_in(bit_pos)bit_pos := bit_pos+1 SEND_STOP_B:txd <= STOP_BITstart_s = 1 cts = 1 bit_pos = 82007/01/16 2007, Masaharu Imai29 RS232C Dsub 9 VHDL 2007/01/16 2007, Masaharu Imai30 R (bps) (R x 16) (kHz) = / = / 21, = / 22, = / 24, = / 29, = / 219, = / 238, = / 357, = / 2115, 2007, Masaharu Imai31RS-232C 33 MHz kbps 2 kbps kbps 3 1:2 9 33,000 / (1, x 2) = 92007/01/16 2007, Masaharu Imai32RS-232C 256 33 MHz3 4 9 1833,3 kHz, kHz, kHz, kHz, kHz.

7 , k Hz 3, kHz1, kHz ( 2:1 2007/01/16 2007, Masaharu Imai33 bps kHz) kHz) (%)300 ,200 ,400 ,800 ,600 ,200 ,400 ,600 ,200 2007, Masaharu Imai34 VHDL RS232C RS232C 2007/01/16 2007, Masaharu Imai35 (1)---- File: Author.

8 Masaharu Imai-- Date: 2004/02/24-- Version : Abstract : generic n bit counter-- Modification History:-- DateBy Version Change Description-- ======================================== =========-- 2004/02/21 MI 2004/02/24 MI was added-- ======================================== =========--2007/01/16 2007, Masaharu Imai36 (2)library ieee;use ;use ;entity counter isgeneric( NBIT: natural := 16; MAX_VAL: natural := 0 );port( clock: in std_logic;reset: in std_logic;count: out std_logic_vector( NBIT-1 downto 0 );carry: out std_logic );end entity counter;2007/01/16 2007, Masaharu Imai37 (3)architecture behavior of counter isbeginprocess( clock, reset )variable count_val: std_logic_vector( NBIT-1 downto 0 );variable carry_val: std_logic;beginif reset = '1' thencount_val := ( others => '0' );carry_val := '0'; elsif clock'event and clock = '1' thencount_val := count_val + 1;if count_val = MAX_VAL thencount_val := ( others => '0' );carry_val := '1';2007/01/16 2007, Masaharu Imai38 (4)elsecarry_val := '0';end if;end if;count <= count_val;carry <= carry_val;end process;end architecture behavior.

9 2007/01/16 2007, Masaharu Imai39RS232C (1)---- File: Author: Masaharu Imai-- Date: 2005/05/09-- Version : Abstract : Clock generator for RS232C ---- clk_out(9): kHz for 300 bps-- clk_out(8): kHz for 600 bps-- clk_out(7): kHz for kbps-- clk_out(6): kHz for kbps-- clk_out(5): kHz for kbps-- clk_out(4): kHz for kbps-- clk_out(3): kHz for kbps-- clk_out(2): kHz for kbps2007/01/16 2007, Masaharu Imai40RS232C (2)-- clk_out(1): kHz for kbps-- clk_out(0) kHz for kbps---- Modification History:-- DateBy Version Change Description-- ======================================== =========-- 2004/11/06 MI 2004/12/23 MI Fixed-- 2005/05/09 MI port renamed-- ======================================== =========--2007/01/16 2007, Masaharu Imai41RS232C (3)library ieee;use ;use ;entity rs232c_clk_gen isport( clk_33 MHz: in std_logic;reset: in std_logic;clk_out: out std_logic_vector( 9 downto 0 ) );end entity rs232c_clk_gen;2007/01/16 2007, Masaharu Imai42RS232C (4)architecture structure of rs232c_clk_gen iscomponent counter isgeneric( NBIT: natural := 16; MAX_VAL: natural := 0 ).

10 Port( clock: in std_logic;reset: in std_logic;count: out std_logic_vector( NBIT-1 downto 0 );carry: out std_logic );end component counter;signal count_1: std_logic_vector( 3 downto 0 );signal count_2: std_logic_vector( 1 downto 0 );signal count_3: std_logic_vector( 1 downto 0 );signal count_4: std_logic_vector( 7 downto 0 );2007/01/16 2007, Masaharu Imai43RS232C (5)signal carry_1: std_logic;signal carry_2: std_logic;signal carry_3: std_logic;signal carry_4: std_logic;beginCNT_1: counter generic map(-- First Base Clock 33 MHz / 9 NBIT => 4, MAX_VAL => 9 )port map(clock => clk_33 MHz,reset => reset,count => count_1,carry => carry_1 );2007/01/16 2007, Masaharu Imai44RS232C (6)CNT_2: counter generic map(-- kHz and K HzNBIT => 2, MAX_VAL => 0)port map(clock => carry_1,reset => reset,count => count_2,carry => carry_2 );CNT_3: counter generic map(-- Second Base Clock NBIT => 2, MAX_VAL => 3)port map(clock => carry_1,reset => reset,count => count_3,carry => carry_3 ).

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