FREE RANGE VHDL

1 Free RANGE vhdl . Bryan Mealy, Fabrizio Tappero . Free RANGE vhdl . Copyright 2018 B. Mealy, F. Tappero Release: Date: 4 January 2018. Book size: 160 mm by 240 mm Pages: 194. The electronic version of this book can be downloaded free of charge from: The authors have taken great care in the preparation of this book, but make no expressed or implied warranty of any kind and assume no responsibility for errors or omissions. No liability is assumed for incidental or consequential damages in connection with or arising out of the use of the information or programs contained in this book. This book is licensed under the Creative Commons Attribution-ShareAlike Unported License, which permits unrestricted use, distribution, adaptation and reproduction in any medium, provided the original work is properly cited.

2 If you build upon this work, you may distribute the resulting work only under the same, similar or a compatible license. To view a copy of this license, visit: Feedback and Contribution We are more than happy to consider your contribution in improving, extending or correcting any part of this book. For any communication or feedback that you might have about the content of this book you can contact the authors using the form at the following address: Cover and Artwork by Robert Ash. To everyone who helped Table of Contents Acknowledgments v Purpose of this book 1. 1 Introduction To vhdl 5. Golden Rules of vhdl 8. Tools Needed for vhdl Development 8. 2 vhdl Invariants 11. Case Sensitivity 11. White Space 11.

3 Comments 12. Parentheses 12. vhdl Statements 13. if, case and loop Statements 13. Identifiers 14. Reserved Words 15. vhdl Coding Style 15. 3 vhdl Design Units 17. Entity 18. vhdl Standard Libraries 22. ii Architecture 23. Signal and Variable Assignments 23. Summary 25. Exercises 26. 4 vhdl Programming Paradigm 29. Concurrent Statements 30. Signal Assignment Operator <= 33. Concurrent Signal Assignment Statements 34. Conditional Signal Assignment when 38. Selected Signal Assignment with select 42. Process Statement 46. Summary 47. Exercises 48. 5 Standard Models in vhdl Architectures 51. Data-flow Style Architecture 52. Behavioral Style Architecture 53. Process Statement 53. Sequential Statements 55.

4 Signal Assignment Statement 57. if Statement 57. case Statement 62. Caveats Regarding Sequential Statements 66. Summary 67. Exercises: Behavioral Modeling 68. 6 vhdl Operators 71. Logical Operators 72. Relational Operators 72. Shift Operator 72. Other Operators 73. Concatenation Operator 74. Modulus and Remainder Operators 74. Review of Almost Everything Up to Now 75. iii 7 Using vhdl for Sequential Circuits 77. Simple Storage Elements Using vhdl 77. Inducing Memory: Data-flow vs. Behavioral Modeling 84. Important Points 85. Exercises: Basic Memory Elements 86. 8 Finite State Machine Design Using vhdl 89. vhdl Behavioral Representation of FSMs 91. One-Hot Encoding for FSMs 101. Important Points 106.

5 Exercises: Behavioral Modeling of FSMs 107. 9 Structural Modeling In vhdl 119. vhdl Modularity with Components 121. Generic Map 129. Important Points 130. Exercises: Structural Modeling 131. 10 Registers and Register Transfer Level 133. Important Points 140. Exercises: Register Transfer Level Circuits 140. 11 Data Objects 143. Types of Data Objects 143. Data Object Declarations 144. Variables and Assignment Operator := 145. Signals vs. Variables 145. Standard Data Types 147. User-Defined Types 147. Commonly Used Types 148. Integer Types 148. signed and unsigned Types 150. std logic Types 151. Important Points 154. iv 12 Looping Constructs 155. for and while Loops 155. for Loops 156. while Loops 158.

6 Loop Control: next and exit Statements 158. 13 Standard digital Circuits in vhdl 161. RET D Flip-flop - Behavioral Model 162. FET D Flip-flop with Active-low Asynchronous Preset - Behavioral Model 162. 8-Bit Register with Load Enable - Behavioral Model 163. Synchronous Up/Down Counter - Behavioral Model 163. Shift Register with Synchronous Parallel Load - Behavioral Model 164. 8-Bit Comparator - Behavioral Model 165. BCD to 7-Segment Decoder - Data-Flow Model 165. 4:1 Multiplexer - Behavioral Model 166. 4:1 Multiplexer - Data-Flow Model 166. Decoder 167. Appendix A vhdl Reserved Words 169. Appendix B Standard vhdl Packages 171. IEEE Standard Libraries 173. Non-standard Libraries 173. Appendix C vhdl Reference Cards 175.

7 Appendix D Contributors to This Book 181. Acknowledgments The authors would like to thank Christina Jarron for her invaluable contri- bution to proofreading this book and for her useful suggestions. Special thanks also to Rob Ash for helping us make the cover of the book distinc- tive with his original artwork. A massive thank you goes to Keith Knowles for his time and effort in reviewing and editing the final draft of this book. Finally, the authors would like to thank all the people who have provided feedback and suggestions. Purpose of this book The purpose of this book is to provide students and young engineers with a guide to help them develop the skills necessary to be able to use vhdl . for introductory and intermediate level digital design.

8 These skills will also give you the ability and the confidence to continue on with vhdl -based digital design. In this way, you will also take steps toward developing the skills required to implement more advanced digital design systems. Although there are many books and on-line tutorials dealing with vhdl , these sources are often troublesome for several reasons. Firstly, much of the information regarding vhdl is either needlessly confusing or poorly written. Material with these characteristics seems to be written from the standpoint of someone who is either painfully intelligent or has forgotten that their audience may be seeing the material for the first time. Secondly, the common approach for most vhdl manuals is to introduce too many topics and a lot of extraneous information too early.

9 Most of this material would best appear later in the presentation. Material presented in this manner has a tendency to be confusing, is easily forgotten if misunderstood or simply is never applied. The approach taken by this book is to provide only what you need to know to quickly get up and running in vhdl . As with all learning, once you have obtained and applied some useful information, it is much easier to build on what you know as opposed to continually adding information that is not directly applicable to the 2. subjects at hand. The intent of this book is to present topics to someone familiar with digital logic design and with some skills in algorithmic programming languages such as Java or C.

10 The information presented here is focused on giving a solid knowledge of the approach and function of vhdl . With a logical and intelligent introduction to basic vhdl concepts, you should be able to quickly and efficiently create useful vhdl code. In this way, you will see vhdl as a valuable design, simulation and test tool rather than another batch of throw-away technical knowledge encountered in some forgotten class or lab. Lastly, vhdl is an extremely powerful tool. The more you understand as you study and work with vhdl , the more it will enhance your learning experience independently of your particular area of interest. It is well worth noting that vhdl and other similar hardware design languages are used to create most of the digital integrated circuits found in the various electronic gizmos that overwhelm our modern lives.