10GBASE-KR FEC Tutorial - IEEE 802

1 IEEE802 Plenary July 200610 GBASE-KR FEC tutorial110 GBASE-KR FEC Tutorial Andre Szczepanek (TI)Ilango Ganga (Intel)Cathy Liu (LSI logic)Magesh Valliappan (Broadcom)IEEE802 Plenary July 200610 GBASE-KR FEC tutorial2 Acknowledgements Jim Hamstra (Flextronics) Winston Mok (PMC Sierra) For the OIF CEI-P FEC, & work on DFE error propagation Andrey Belogolovy (Intel) Andrey Ovchinnikov (Intel) For Code selection and simulation Luke Chang (Intel) Fulvio Spagna (Intel) Joe Caroselli (LSI Logic) For TF contributionsIEEE802 Plenary July 200610 GBASE-KR FEC tutorial3 Agenda Introduction FEC requirements & code selection DFE Error propagation Simulated Performance of the FEC Ease of Implementation ConclusionIEEE802 Plenary July 200610 GBASE-KR FEC tutorial4 IntroductionWhat is the 10 GBASE-KR FEC ?

2 An optional sub-layer of (Backplane Ethernet) A generic sublayer to the 10 GBASE-R PCS Could be used by other clauses But only 10 GBASE-KR has the AN support to enable it Transports 10 GBASE-R 64b/66b codewords in FEC protected blocks Within the same data-rate A lightweight FEC, with limited coding gain, that is simple to implement Targeted at single burst error correctionIEEE802 Plenary July 200610 GBASE-KR FEC FEC requirements & code selectionIlango Ganga, IntelIEEE802 Plenary July 200610 GBASE-KR FEC tutorial6 Objectives FEC to provide additional gain BER objective of 10-12or better on a broader set of backplane channels Improve overall system reliability by significantly lowering BER Improve Mean Time to False Packet Acceptance (MTTFPA) requirements for 10 GbE Minimum changes to existing sublayers Locate between PCS & PMA and be compatible with existing PCS (clause 49) & PMA (clause 51) No increase in baud rate or decrease in payload rate Low overhead (latency/area/power)

3 Negotiate FEC capability through Auto-NegotiationIEEE802 Plenary July 200610 GBASE-KR FEC tutorial7 FEC overview Binary burst error correction code (2112, 2080) Shortened cyclic code Systematic: 2080 bits of payload and 32 bits of overhead Can correct burst errors of up to 11 bits Modulation: NRZ Symbol rate: Compression and usage of 32 sync bits from 64B/66B blocks Compatibility with Clause 49 & Clause 51 (use of 16-bit data path as in XSBI) Synchronization at FEC block boundariesIEEE802 Plenary July 200610 GBASE-KR FEC tutorial8 Codes comparison Codes with 32 parity check bits were compared Binary burst error correction code (2112,2080), with Meggitt decoder RS(255,251) over GF(28) with Berlekamp decoder Coding gain of binary code is better For the same coding gain (or better) RS codes should have 40 redundant bits RS over GF(210)

4 With 2 parity check symbols Can be implemented with a Meggittdecoder Significantly simpler than Berlekampdecoders for RS codes3132333435363710-910-810-710-610-51 0-410-310-2 SNR, dBBERC hannel T1: BER with optimal (3,5)DFEU ncodedQC(2112,2080) binaryRS(255,251) over GF(28)IEEE802 Plenary July 200610 GBASE-KR FEC tutorial9 FEC code description The (2112, 2080) burst error correction code isаshortened cyclic code with 32 redundant bits Guaranteed errors burst length that can be corrected is t = 11 bits It is a systematic code well suited for correction of the burst errors, typical in a backplane channel resulting from DFE error propagation The (2112, 2080) code was constructed by shortening of cyclic code (42987, 42955)

5 Generator polynomial g(x)=x32+x23+x21+x11+x2+1 For (2112, 2080) code encoder: systematic, represented by LFSR of length 32 decoder: Meggitt decoder for shortened cyclic codes detector: syndrome calculation PN-2112 bit sequence Generated by scrambler polynomial from Clause 49 r(x)= x58+x39+1 with initial state of x57=1 and xi-1=xi(XOR)1 or binary For every codeword PN-2112 sequence is returned to its initial state Scrambling with PN-2112 sequence is necessary to maintain DC balance and to ensure FEC block sync (ensures any shift in code word is not equal to another)IEEE802 Plenary July 200610 GBASE-KR FEC tutorial10 FEC functional block Relationship to PCS/PMA sublayersENCODESCRAMBLEFEC(2112,2080)

6 EncoderBLOCK SYNCFEC(2112,2080) decoder and block syncDESCRAMBLEDECODEPMA SUBLAYERPCS transmitPCS receiveMDIPMA service interfaceXGMIIPCSC lause49 PMAC lause 51 GEARBOXBER & SYNC HEADER MONITOR-- All from Clause 49, Figure 49-4-- New blocksFEC Clause 74 XSBIIEEE802 Plenary July 200610 GBASE-KR FEC tutorial11 FEC sublayer Transparent to PCS and PMA (clauses 49 & 51) 16-bit input and 16-bit output interface (optional) Operates on 64b/66b block boundaries Uses shortened cyclic (2112, 2080) burst error correction code For 32 parity check bits 1 of the 2 sync bits from 32 64B/66B blocks is used Encoding latency is 32 bits Establishes synchronization at FEC block boundaries (32 64B/66B blocks) Scrambling with PN-2112 sequence is necessary to maintain DC balance and to ensure FEC block sync (any shift in code word is not equal to another) Provides - dB energy gainIEEE802 Plenary July 200610 GBASE-KR FEC tutorial12 Block diagram of FEC sublayerFEC (2112,2080) encodingFEC (2 11 2, 208 0) E ncod er6 4b /66 b b locks< 65.

7 0> g(x)FEC 32-bit Parity Ge ne ra torCompress S ync bits (64 b/ 66b to 65 bit blocks)65 b bl ocks PN-21 12 Gen erat orMe ssag e o r Parity S elect orReverse Gearboxtx_d at a- gr ou p< 15 :0> ( fr om PCS)tx_d ata -g r oup < 15: 0> ( to PM A)p( x)c(x)m(x)r( x )FEC (2112,2080) decodingFEC (2112,2080) Decoder P N- 2 112 Ge ne ra torrx_ da ta- gr o up< 1 5:0 > (fr o m P MA ) FEC Block Syn cr(x)6 5b bl ocks Recon struct 64b/66b blocks( 21 12 ,20 80 ) De c od er FEC E rr or Mo n i t o rrx_data-group<15:0> (to PCS)De s c ra m bl ed da taIEEE802 Plenary July 200610 GBASE-KR FEC tutorial13 FEC block format Payload words carry the 10 GBASE-R scrambled payload words Tn = Transcode bit carries the state of the 10 GBASE-R sync bits for the associated payload word Sync bits are compressed toаsingle bit then scrambled to ensure DC balance 64b/66b sync bits are either 10 or 01 hence can be reconstructed from the T bit Synchronization is achieved at FEC block level Block has the same overhead as 64B/66B encodingT064 Bit Payload Word 0T164 Bit Payload Word 1T264

8 Bit Payload Word 2T364 Bit Payload Word 3T464 Bit Payload Word 4T564 Bit Payload Word 5T664 Bit Payload Word 6T764 Bit Payload Word 7T864 Bit Payload Word 8T964 Bit Payload Word 9T1064 Bit Payload Word 10T1164 Bit Payload Word 11T1264 Bit Payload Word 12T1364 Bit Payload Word 13T1464 Bit Payload Word 14T1564 Bit Payload Word 15T1664 Bit Payload Word 16T1764 Bit Payload Word 17T1864 Bit Payload Word 18T1964 Bit Payload Word 19T2064 Bit Payload Word 20T2164 Bit Payload Word 21T2264 Bit Payload Word 22T2364 Bit Payload Word 23T2464 Bit Payload Word 24T2564 Bit Payload Word 25T2664 Bit Payload Word 26T2764 Bit Payload Word 27T2864 Bit Payload Word 28T2964 Bit Payload Word 29T3064 Bit Payload Word 30T3164 Bit Payload Word 3132 parity bitsTotal Block length = (32 x 65) + 32 = 2112 bits IEEE802 Plenary July 200610 GBASE-KR FEC tutorial14 Transmit bit orderingFEC Tran smit bit ordering64b/66b outputS0S 1S2S3S 4S5S 6S 707S0S1S2S3S4S5S6S707 Output of Transcoder 65b Block 0064 FEC block64b/66b to 65b TranscoderPN- 2112 Scrambl er Sync headerfunctiontx_data-group<0> (PMA)

9 Tx_data-group<15> (PMA)Transcode bit TFEC (2112, 2080) EncoderAggregate 32 65b bl ocks pl us 32b Pari ty65b Bl ock 106465b Bl ock 3106432b Par ity031tx_data-group<0> (PCS)t x_ d at a - gr ou p<1 5> ( P CS)Reverse Gearbox functionof PCS function0110= XOR bi t T = XOR Plenary July 200610 GBASE-KR FEC tutorial15 Use conventional n/m serial locking techniques Similar to 64B/66B word sync State Machine Requires up to 2112 bit shifts to establish synchronization Uses error detection properties of (2112,2080) decoder and PN-2112 sequence for frame delineation Wrong synchronization probability is lower than 10-8 Loss of sync is reported if parity check failed for m >= 8 consecutive frames Sync is reported if parity check passed for n >= 4 consecutive framesFEC sublayer synchronizationFEC (2112,2080) block sync and decod ingInput Bit Stream FEC BLO CK SYNC BUFFER FEC (2112,2080) DECODE PA R I TY M AT C HIs Decode successful?

10 LOAD N EXT BIT AND SH IF T CANDIDAT E