© Copyright 2013 2016 Xilinx

1 Copyright 2013 2016 Xilinx . Copyright 2013 2016 2 Kintex UltraScale FPGAsDevice NameKU025(1)KU035KU040KU060KU085KU095KU1 15 Logic ResourcesSystem Logic Cells (K) 3184445307261,0881,1761,451 CLB Flip-Flops290,880406,256 484,800 663,360 995,040 1,075,200 1,326,720 CLB LUTs145,440203,128242,400331,680497,5205 37,600663,360 Memory ResourcesMaximum Distributed RAM(Kb)4,2305,908 7,050 9,180 13,770 4,800 18,360 Block RAM/FIFO w/ECC (36Kb each)3605406001,0801,6201,6802,160 Block RAM/FIFO (18Kb each)7201,080 1,200 2,160 3,240 3,360 4,320 Total Block RAM(Mb) ResourcesCMT (1 MMCM,2 PLLs)610 10 12 2216 24 I/O DLL24404048566464I/O ResourcesMaximum Single-Ended HP I/Os208416 416 520 572 650676 Maximum Differential HP I/O Pairs96192192240264288312 Maximum Single-Ended HR I/Os104104 104 104 104 52 156 Maximum Differential HR I/O Pairs48484848562472 Integrated IP ResourcesDSP Slices1,1521,700 1,920 2,760 4,100 768 5,520 System Monitor1111212 PCIe Gen1/2/312 3 3 4 4 6 Interlaken00 00020 100G Ethernet0000020 Transceivers (GTH/GTY) 121620325664(2)64 Speed GradesCommercial-1-1-1-1-1-1-1 Extended-2-2 -3-2 -3-2 -3-2 -3-2-2 -3 Industrial-1-2-1 -1L -2-1 -1L -2-1 -1L -2-1 -1L -2-1 -2-1 -1L -2 PackageFootprint(3, 4, 5, 6)Package Dimensions (mm)

2 HR I/O, HP I/O, GTH/GTYA784(7)23x23(8)104, 364, 8104, 364, 8A676(7)27x27104, 208, 16104, 208, 16A900(7)31x31104, 364, 16104, 364, 16A115635x35104, 208, 12104, 416, 16104, 416, 20104, 416, 2852, 468, 28A151740x40104, 520, 32104, 520, 48104, 520, 48 Footprint Compatible with Virtex UltraScale DevicesC151740x4052, 468, 40D151740x40104, 234, , 572, 4452, 650, 48104, 598, , 676, , 650, 64104, 598, 64D192445x45156, 676, 52F192445x45104, 520, 56104, 624, 64 Notes: advanced configuration features are not supported in the KU025. Refer to the Configuring FPGAs section in DS890, UltraScale Architecture and Product transceivers in KU095 devices support data rates up to with the same package footprint designator, , A2104, are footprint compatible with all other UltraScale devices with the same sequence.

3 See the migration tablefor details on inter-family achievable performance is device and package dependent; consult the associated data sheet for full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product UG575, UltraScale Architecture Packaging and Pinouts User Guide for more transceivers in A784, A676, and A900 packages support data rates up to ball pitch. All other packages listed 1mm ball pitch. Copyright 2013 2016 3 Virtex UltraScale FPGAsDevice NameXCVU065 XCVU080 XCVU095 XCVU125 XCVU160 XCVU190 XCVU440 Logic ResourcesSystem Logic Cells (K) 7839751,1761,5672,0272,3505,541 CLB Flip-Flops716,160891,4241,075,2001,432,3 201,852,8002,148,4805,065,920 CLB LUTs358,080445,712537,600716,160926,4001 ,074,2402,532,960 Memory ResourcesMaximum Distributed RAM (Kb)4,8303,9804,8009,66012,69014,49028,7 10 Block RAM/FIFO w/ECC (36Kb each)1,2601,4211,7282,5203,2763,7802,520 Block RAM/FIFO (18Kb each)2,5202,8423,4565,0406,5527,5605,040 Total Block RAM (Mb) ResourcesCMT (1 MMCM, 2 PLLs)

4 10161620283030I/O DLL40646480120120120 TransceiverFractional PLL5881013150I/O ResourcesMaximum Single-Ended HP I/Os4687807807806506501,404 Maximum Differential HP I/O Pairs216360360360300300648 Maximum Single-Ended HR I/Os52525252525252 Maximum Differential HR I/O Pairs24242424242424 Integrated IP ResourcesDSP Slices6006727681,2001,5601,8002,880 System Monitor1112333 PCIe Gen1/2/32444466 Interlaken3666890100G Ethernet3446993 GTH Transceivers20323240526048 GTY Transceivers2032324052600 Speed GradesCommercial -1 Extended-1H-2 -3-1H-2 -3-1H-2 -3-1H-2 -3-1H-2 -3-1H-2 -3-2 -3 Industrial-1 -2-1-2-1-2-1-2-1-2-1-2-1 -2 PackageFootprint(1, 2, 3)Package Dimensions (mm)HR I/O, HP I/O, GTH , GTY Compatible with Kintex UltraScale DevicesC151740x4052, 468, 20, 2052, 468, 20, 2052, 468, 20, 20D151740x4052, 286, 32, 3252, 286, 32, 3252, 286, 40, , 650, 32, 1652, 650, 32, 1652, 650, 36, , 780, 28, 2452, 780, 28, 2452, 780, 28, , 650, 32, 3252, 650, 32, 3252, 650, 40, 3652, 650, 40, 3652, 650, 40, , 364, 32, 3252, 364, 40, 4052, 364, 52, 5252, 364, 52, 52B237750x5052, 1248, 36, , 448, 60, 60A289255x5552, 1404, 48, 0 Notes: with the same package footprint designator, , A2104, are footprint compatible with all other UltraScale devices with the same sequence.

5 See the migration tablefor details on inter-family full part number details, see the Ordering Information section in DS890, UltraScale Architecture and Product UG575, Kintex UltraScale and Virtex UltraScale FPGAs Packaging and Pinouts User Guide for more information. Copyright 2013 2016 4 UltraScale Device Ordering InformationXilinx CommercialUltraScaleV: VirtexK: KintexF: LidL: Lid SSIB: LidlessValue IndexF: Flip-Chip ( )S: Flip-Chip ( )V: RoHS 6/6G: RoHS 6/6 w/exemption 15 PackageDesignatorSpeed Grade-1 = Slowest-L1 = Low Power(Kintex only)-H1 = Slowest or Mid(Virtex only)-2 = Mid -3 = FastestFootprintTemperature Grade(C, E, I)C = Commercial (Tj = 0 C to +85 C)E = Extended (Tj = 0 C to +100 C)I = Industrial (Tj = 40 C to +100 C)PackagePin CountXCVU###-1 FLVA####CImportant.

6 Verify all data in this document with the device data sheets found at valid part/package combinations, go to DS890, UltraScale Architecture and Product Overview: Device-Package Combinations and Maximum I/Os Tables Copyright 2013 2016 DeviceFootprintCompatibilityHR I/O, HP I/O, GTH ; GTY (mm) , 208, 12, 0 XCKU035104, 364, 8, 0104, 208,16, 0104, 364,16, 0104, 416,16, 0 XCKU040104, 364, 8, 0104, 208,16, 0104, 364,16, 0104, 416,20, 0 XCKU060104, 416, 28, 0104, 520, 32, 0 XCKU085N/A104, 520, 48, 0104, 572, 44, 0 XCKU09552, 468, 20, 8(1)N/A52, 468, 20, 20(1)52, 650, 32, 16(1)XCKU115104,520, 48, 0N/A104, 234, 64, 0104, 598, 52, 0 XCVU06552, 468,20, 20N/AN/AXCVU08052, 468,20, 2052, 286, 32, 3252, 650,32, 16 XCVU09552, 468,20, 2052, 286, 32, 3252, 650,32, 16 XCVU12552, 286, 40, 3252, 650,36, 16 Page 523mm.

7 Verify all data in this document with the device data sheets found at transceivers in KU095 devices support data rates up to Refer to data sheet for compatibility is indicated by shading per column. Copyright 2013 2016 DeviceFootprintCompatibilityHR I/O, HP I/O, GTH ; GTY Dimensions (mm) , 520, 56, 0 XCKU095N/A52, 650, 32, 32(1)XCKU115156, 676, 52, 0104, 624, 64, 0156, 676, 52, 0104, 598, 64, 0 XCVU065N/AN/AXCVU08052, 780, 28, 2452, 650, 32, 32 XCVU09552, 780, 28, 2452, 650, 32, 3252, 364, 32, 32 XCVU12552, 780, 28, 2452, 650, 40, 3652, 364, 40, 40 XCVU16052, 650, 40, 3652, 364, 52, 52 XCVU19052, 650, 40, 3652, 364, 52, 520, 448, 60, 60 XCVU44052, 1248, 36, 052, 1404, 48, 0 Page 645mm 55 transceivers in KU095 devices support data rates up to Refer to data sheet for : Verify all data in this document with the device data sheets found at compatibility is indicated by shading per column.

8 Copyright 2013 2016 7 UltraScale Architecture Migration TablePkgmmKintex UltraScale KintexUltraScale+ Virtex UltraScaleVirtexUltraScale+ (1) (1) (1) body size of the VU13P device in the A2104, B2104, and C2104 packages is These packages are footprint compatible with the corresponding body size UG583, UltraScale Architecture PCB Design User Guide for important migration details. UltraScale and UltraScale+ families provide footprint compatibility to enable users to migrate designs from one device or family to another. Any two packages with the same footprint identifier code are footprint compatible. Copyright 2013 2016 8 Digital Signal Processing MetricsUltraScale architecture further enhances the Xilinx DSP48 slice with features designed to allow users to do more calculations in fewer DSP resources, enhancing both device utilization and performance.

9 Examples include wider multipliers for floating point calculations, wide XOR functions for ECC, CRC, and EFEC, and pre-adder squaring for rounding algorithms. Speed grade-1-2-3 FMAX[MHz]594661741 Max GMAC/s 6558729781811920170027604100552060067276 8120015601800768 XCKU035 XCKU040 XCKU060 XCKU085 XCKU095 XCKU115 XCVU065 XCVU080 XCVU095 XCVU125 XCVU160 XCVU190 DSP Slice CountFor more information, refer to: UG579, UltraScale Architecture DSP Slice User GuideImportant: Verify all data in this document with the device data sheets found at Copyright 2013 2016 9 Block RAM MetricsUltraScale architecture block RAM adds new features to increase performance, device utilization, and power efficiency.

10 These new features are designed to provide highly efficient solutions for applications in the Wireless, Wired, Video, and Signal Processing markets by offering hardened memory cascade to reduce fabric use and increase performance, and flexible hard FIFO and user accessible dynamic power control to reduce power. Speed grade-1-2-3 True dual-port Block RAM FMAX [MHz]525585660 For more information, refer to: UG573, UltraScale Architecture Memory Resources User Guide Important: Verify all data in this document with the device data sheets found at RAM Capacity (Mb)133 XCVU19013 XCKU025 Copyright 2013 2016 10 High-Speed Serial TransceiversFor high bandwidth applications, including 500Gb/s, 400Gb/s, and 100Gb/s line cards, serial data transmission across backplanes and longer distances is becoming increasingly important.