29.2 Numeric, Pointer, Bit Field, and String Data Types

1 Embedded Pentium Processor Family 29-505 Data Types and Addressing Modes29 This section describes data Types and addressing modes available to programmers of the Intel Architecture processors. Data TypesThe fundamental data Types of the Intel Architecture are bytes, words, doublewords, and quadwords (see Figure 29-1). A byte is eight bits, a word is 2 bytes (16 bits), a doubleword is 4 bytes (32 bits), and a quadword is 8 bytes (64 bits).Figure 29-2 shows the byte order of each of the fundamental data Types when referenced as operands in memory. The low byte (bits 0 through 7) of each data type occupies the lowest address in memory and that address is also the address of the of Words, Doublewords, and QuadwordsWords, doublewords, and quadwords do not need to be aligned in memory on natural boundaries. (The natural boundaries for words, double words, and quadwords are even-numbered addresses, addresses evenly divisible by four, and addresses evenly divisible by eight, respectively.)

2 However, to improve the performance of programs, data structures (especially stacks) should be aligned on natural boundaries whenever possible. The reason for this is that the processor requires two memory accesses to make an unaligned memory access; whereas, aligned accesses require only one memory access. A word or doubleword operand that crosses a 4-byte boundary or a quadword operand that crosses an 8-byte boundary is considered unaligned and requires two separate memory bus cycles to access it; a word that starts on an odd address but does not cross a word boundary is considered aligned and can still be accessed in one bus 29-1. Fundamental Data Types063 Quadword0 Word310 Doubleword150 Byte778 NLow WordHigh WordLow DoublewordHigh Doubleword15163132N+1 NNN+2N+4 NLowByteHighByte29-506 Embedded Pentium Processor Family Data Types and Addressing , Pointer, Bit Field, and String Data TypesAlthough bytes, words, and doublewords are the fundamental data Types of the Intel Architecture, some instructions support additional interpretations of these data Types to allow operations to be performed on numeric data Types (signed and unsigned integers and BCD integers).

3 See Figure 29-3. Also, some instructions recognize and operate on additional pointer, bit field, and String data Types . The following sections describe these additional data are signed binary numbers held in a byte, word, or doubleword. All operations assume a two s complement representation. The sign bit is located in bit 7 in a byte integer, bit 15 in a word integer, and bit 31 in a doubleword integer. The sign bit is set for negative integers and cleared for positive integers and zero. Integer values range from 128 to +127 for a byte integer, from 32,768 to +32,767 for a word integer, and from 231 to +231 1 for a doubleword 29-2. Bytes, Words, Doublewords and Quadwords in MemoryEHDH7 AHCHFEHBH06 HAH36H9H1FH8HA4H7H23H6H0BH5H4H3H74H2 HCBH1H31H0 HQuadword at Address 6 HContains 7 AFE06361FA4230 BHDoubleword at Address AHContains 7 AFE0636 HWord at Address BHContains FE06 HByte at Address 9 HContains 1 FHWord at Address 6 HContains 230 BHWord at Address 1 HContains CB31 HWord at Address 2 HContains 74 CBHE mbedded Pentium Processor Family 29-507 Data Types and Addressing IntegersUnsigned integers are unsigned binary numbers contained in a byte, word, or doubleword.

4 Unsigned integer values range from 0 to 255 for an unsigned byte integer, from 0 to 65,535 for an unsigned word integer, and from 0 to 232 1 for an unsigned doubleword integer. Unsigned integers are sometimes referred to as 29-3. Numeric, Pointer, and Bit Field Data Types047 Far Pointer or Logical AddressSegment Selector32 31 Offset0 Near Pointer31 Offset or Linear AddressBit FieldField Length0 Doubleword Unsigned Integer310 Packed BCD Integers7 BCDBCDBCDBCDBCDBCD34..0 BCD Integers7 BCDXBCDXBCDX34..0 Word Unsigned Integer150 Byte Unsigned Integer70 Doubleword Signed Integer31300 Word Signed Integer15140 Byte Signed Integer76 SignSignSignLeastBitSignificant29-508 Embedded Pentium Processor Family Data Types and Addressing IntegersBinary-coded decimal integers (BCD integers) are unsigned 4-bit integers with valid values ranging from 0 to 9. BCD integers can be unpacked (one BCD digit per byte) or packed (two BCD digits per byte).

5 The value of an unpacked BCD integer is the binary value of the low half-byte (bits 0 through 3). The high half-byte (bits 4 through 7) can be any value during addition and subtraction, but must be zero during multiplication and BCD integers allow two BCD digits to be contained in one byte. Here, the digit in the high half-byte is more significant than the digit in the low are addresses of locations in memory. The Pentium Pro processor recognizes two Types of pointers: a near pointer (32 bits) and a far pointer (48 bits). A near pointer is a 32-bit offset (also called an effective address) within a segment. Near pointers are used for all memory references in a flat memory model or for references in a segmented model where the identity of the segment being accessed is implied. A far pointer is a 48-bit logical address, consisting of a 16-bit segment selector and a 32-bit offset. Far pointers are used for memory references in a segmented memory model where the identity of a segment being accessed must be specified explicitly.

6 FieldsA bit field is a contiguous sequence of bits. It can begin at any bit position of any byte in memory and can contain up to 32 are continuous sequences of bits, bytes, words, or doublewords. A bit String can begin at any bit position of any byte and can contain up to 232 1 bits. A byte String can contain bytes, words, or doublewords and can range from zero to 232 1 bytes (4 gigabytes). Data TypesThe processor s floating-point instructions recognize a set of real, integer, and BCD integer data Types . See Floating-Point Data Types and Formats, for a description of FPU data Technology Data TypesIntel Architecture processors that implement the Intel MMX technology recognize a set of packed 64-bit data Types . See MMX Data Types , for a description of the MMX data AddressingAn Intel Architecture machine-instruction acts on zero or more operands. Some operands are specified explicitly in an instruction and others are implicit to an instruction.

7 An operand can be located in any of the following places:Embedded Pentium Processor Family 29-509 Data Types and Addressing Modes The instruction itself (an immediate operand). A register. A memory location. An I/O OperandsSome instructions use data encoded in the instruction itself as a source operand. These operands are called immediate operands (or simply immediates). For example, the following ADD instruction adds an immediate value of 14 to the contents of the EAX register:ADD EAX, 14 All the arithmetic instructions (except the DIV and IDIV instructions) allow the source operand to be an immediate value. The maximum value allowed for an immediate operand varies among instructions, but can never be greater than the maximum value of an unsigned doubleword integer (232). OperandsSource and destination operands can be located in any of the following registers, depending on the instruction being executed: The 32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP).

8 The 16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, or BP). The 8-bit general-purpose registers (AH, BH, CH, DH, AL, BL, CL, or DL). The segment registers (CS, DS, SS, ES, FS, and GS). The EFLAGS register. System registers, such as the global descriptor table (GDTR) or the interrupt descriptor table register (IDTR).Some instructions (such as the DIV and MUL instructions) use quadword operands contained in a pair of 32-bit registers. Register pairs are represented with a colon separating them. For example, in the register pair EDX:EAX, EDX contains the high order bits and EAX contains the low order bits of a quadword operand. Several instructions (such as the PUSHFD and POPFD instructions) are provided to load and store the contents of the EFLAGS register or to set or clear individual flags in this register. Other instructions (such as the Jcc instructions) use the state of the status flags in the EFLAGS register as condition codes for branching or other decision making processor contains a selection of system registers that are used to control memory management, interrupt and exception handling, task management, processor management, and debugging activities.

9 Some of these system registers are accessible by an application program, the operating system, or the executive through a set of system instructions. When accessing a system register with a system instruction, the register is generally an implied operand of the Pentium Processor Family Data Types and Addressing OperandsSource and destination operands in memory are referenced by means of a segment selector and an offset (see Figure 29-4). The segment selector specifies the segment containing the operand and the offset (the number of bytes from the beginning of the segment to the first byte of the operand) specifies the linear or effective address of the a Segment SelectorThe segment selector can be specified either implicitly or explicitly. The most common method of specifying a segment selector is to load it in a segment register and then allow the processor to select the register implicitly, depending on the type of operation being performed.

10 The processor automatically chooses a segment according to the rules given in Table 29-1. When storing data in or loading data from memory, the DS segment default can be overridden to allow other segments to be accessed. Within an assembler, the segment override is generally handled with a colon : operator. For example, the following MOV instruction moves a value from register EAX into the segment pointed to by the ES register. The offset into the segment is contained in the EBX register:MOV ES:[EBX], EAX;(At the machine level, a segment override is specified with a segment-override prefix, which is a byte placed at the beginning of an instruction.) The following default segment selections cannot be overridden: Instruction fetches must be made from the code segment. Destination strings in String instructions must be stored in the data segment pointed to by the ES register. Push and pop operations must always reference the SS 29-4.