3V 128M-BIT SERIAL FLASH MEMORY WITH …

1 W25Q128JV Publication Release Date: March 27, 2018 Revision F 3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI For Industrial & Industrial Plus Grade W25Q128JV - 1 - Table of Contents 1. GENERAL DESCRIPTIONS .. 4 2. FEATURES .. 4 3. PACKAGE TYPES AND PIN CONFIGURATIONS .. 5 Pin Configuration SOIC 208-mil .. 5 Pad Configuration WSON 6x5-mm/ 8x6-mm .. 5 Pin Description SOIC 208-mil, WSON 6x5-mm / 8x6-mm .. 5 Pin Configuration SOIC 300-mil .. 6 Pin Description SOIC 300-mil .. 6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) .. 7 Ball Description TFBGA 8x6-mm .. 7 Ball Configuration WLCSP .. 8 Ball Description WLCSP24 .. 8 4. PIN DESCRIPTIONS .. 9 Chip Select (/CS) .. 9 SERIAL Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .. 9 Write Protect (/WP) .. 9 HOLD (/HOLD).

2 9 SERIAL Clock (CLK) .. 9 Reset (/RESET) .. 9 5. BLOCK DIAGRAM .. 10 6. FUNCTIONAL DESCRIPTIONS .. 11 Standard SPI Instructions .. 11 Dual SPI Instructions .. 11 Quad SPI Instructions .. 11 Software Reset & Hardware /RESET pin .. 11 Write Protection .. 12 Write Protect Features .. 12 7. STATUS AND CONFIGURATION REGISTERS .. 13 Status Registers .. 13 Erase/Write In Progress (BUSY) Status Only .. 13 Write Enable Latch (WEL) Status Only .. 13 Block Protect Bits (BP2, BP1, BP0) Volatile/Non-Volatile Writable .. 13 Top/Bottom Block Protect (TB) Volatile/Non-Volatile Writable .. 14 Sector/Block Protect Bit (SEC) Volatile/Non-Volatile Writable .. 14 Complement Protect (CMP) Volatile/Non-Volatile Writable .. 14 W25Q128JV Publication Release Date: March 27, 2018 - 2 - Revision F Status Register Protect (SRP, SRL) Volatile/Non-Volatile Writable.

3 15 Erase/Program Suspend Status (SUS) Status 16 Security Register Lock Bits (LB3, LB2, LB1) Volatile/Non-Volatile OTP Writable .. 16 Quad Enable (QE) Volatile/Non-Volatile Writable .. 16 Write Protect Selection (WPS) Volatile/Non-Volatile Writable .. 17 Output Driver Strength (DRV1, DRV0) Volatile/Non-Volatile Writable .. 17 Reserved Bits Non Functional .. 17 W25Q128JV Status Register MEMORY Protection (WPS = 0, CMP = 0) .. 18 W25Q128JV Status Register MEMORY Protection (WPS = 0, CMP = 1) .. 19 W25Q128JV Individual Block MEMORY Protection (WPS=1) .. 20 8. INSTRUCTIONS .. 21 Device ID and Instruction Set Tables .. 21 Manufacturer and Device Identification .. 21 Instruction Set Table 1 (Standard SPI Instructions)(1).. 22 Instruction Set Table 2 (Dual/Quad SPI Instructions) .. 23 Notes: .. 23 Instruction Descriptions.

4 24 Write Enable (06h) .. 24 Write Enable for Volatile Status Register (50h) .. 24 Write Disable (04h) .. 25 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) .. 25 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) .. 26 Read Data (03h) .. 28 Fast Read (0Bh) .. 29 Fast Read Dual Output (3Bh) .. 30 Fast Read Quad Output (6Bh) .. 31 Fast Read Dual I/O (BBh) .. 32 Fast Read Quad I/O (EBh) .. 33 Set Burst with Wrap (77h) .. 35 Page Program (02h) .. 36 Quad Input Page Program (32h) .. 37 Sector Erase (20h) .. 38 32KB Block Erase (52h) .. 39 64KB Block Erase (D8h) .. 40 Chip Erase (C7h / 60h) .. 41 Erase / Program Suspend (75h) .. 42 Erase / Program Resume (7Ah) .. 43 Power-down (B9h) .. 44 Release Power-down / Device ID (ABh) .. 45 Read Manufacturer / Device ID (90h).

5 46 W25Q128JV - 3 - Read Manufacturer / Device ID Dual I/O (92h) .. 47 Read Manufacturer / Device ID Quad I/O (94h) .. 48 Read Unique ID Number (4Bh).. 49 Read JEDEC ID (9Fh) .. 50 Read SFDP Register (5Ah) .. 51 Erase Security Registers (44h) .. 52 Program Security Registers (42h) .. 53 Read Security Registers (48h) .. 54 Individual Block/Sector Lock (36h) .. 55 Individual Block/Sector Unlock (39h) .. 56 Read Block/Sector Lock (3Dh) .. 57 Global Block/Sector Lock (7Eh) .. 58 Global Block/Sector Unlock (98h) .. 58 Enable Reset (66h) and Reset Device (99h) .. 59 9. ELECTRICAL CHARACTERISTICS .. 60 Absolute Maximum Ratings (1) .. 60 Operating 60 Power-Up Power-Down Timing and Requirements .. 61 DC Electrical Characteristics- .. 62 AC Measurement Conditions .. 63 AC Electrical Characteristics(6) .. 64 SERIAL Output Timing.

6 66 SERIAL Input Timing .. 66 /WP Timing .. 66 10. PACKAGE SPECIFICATIONS .. 67 8-Pin SOIC 208-mil (Package Code S) .. 67 16-Pin SOIC 300-mil (Package Code F) .. 68 8-Pad WSON 6x5-mm (Package Code P) .. 69 8-Pad WSON 8x6-mm (Package Code E) .. 70 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 ball array) .. 71 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 ball array) .. 72 24-Ball WLCSP (Package Code Y) .. 73 11. ORDERING INFORMATION .. 74 Valid Part Numbers and Top Side Marking .. 75 12. REVISION HISTORY .. 77 W25Q128JV Publication Release Date: March 27, 2018 - 4 - Revision F 1. GENERAL DESCRIPTIONS The W25Q128JV ( 128M-BIT ) SERIAL FLASH MEMORY provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary SERIAL FLASH devices.

7 They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single to power supply with current consumption as low as 1 A for power-down. All devices are offered in space-saving packages. The W25Q128JV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128JV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.) The W25Q128JV supports the standard SERIAL Peripheral Interface (SPI), Dual/Quad I/O SPI: SERIAL Clock, Chip Select, SERIAL Data I/O0 (DI), I/O1 (DO), I/O2 and I/O3.

8 SPI clock frequencies of W25Q128JV of up to 133 MHz are supported allowing equivalent clock rates of 266 MHz (133 MHz x 2) for Dual I/O and 532 MHz (133 MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel FLASH memories. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP, and a 64-bit Unique SERIAL Number and three 256-bytes Security Registers. 2. FEATURES New Family of SpiFlash Memories W25Q128JV: 128M-BIT / 16M-byte Standard SPI: CLK, /CS, DI, DO Dual SPI: CLK, /CS, IO0, IO1 Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 Software & Hardware Reset(1) Highest Performance SERIAL FLASH 133 MHz Single, Dual/Quad SPI clocks 266/532 MHz equivalent Dual/Quad SPI 66MB/S continuous data transfer rate Min.

9 100K Program-Erase cycles per sector More than 20-year data retention Efficient Continuous Read Continuous Read with 8/16/32/64-Byte Wrap As few as 8 clocks to address MEMORY Allows true XIP (execute in place) operation Low Power, Wide Temperature Range Single to supply <1 A Power-down (typ.) -40 C to +85 C operating range -40 C to +105 C operating range Flexible Architecture with 4KB sectors Uniform Sector/Block Erase (4K/32K/64K-Byte) Program 1 to 256 byte per programmable page Erase/Program Suspend & Resume Advanced Security Features Software and Hardware Write-Protect Power Supply Lock-Down Special OTP protection Top/Bottom, Complement array protection Individual Block/Sector array protection 64-Bit Unique ID for each device Discoverable Parameters (SFDP) Register 3X256-Bytes Security Registers with OTP locks Volatile & Non-volatile Status Register Bits Space Efficient Packaging 8-pin SOIC 208-mil 16-pin SOIC 300-mil (additional /RESET pin) 8-pad WSON 6x5-mm / 8x6-mm 24-ball TFBGA 8x6-mm (6x4/5x5 ball array) 24-ball WLCSP Contact Winbond for KGD and other options Note: 1.

10 Hardware /RESET pin is only available on TFBGA or SOIC16 packages W25Q128JV - 5 - 3. PACKAGE TYPES AND PIN CONFIGURATIONS Pin Configuration SOIC 208-mil 12348765/CSDO (IO1)/WP (IO2)GNDVCC/HOLD or /RESET(IO3)DI (IO0)CLKTop View Figure 1a. W25Q128JV Pin Assignments, 8-pin SOIC 208-mil (Package Code S) Pad Configuration WSON 6x5-mm/ 8x6-mm 1234/CSDO (IO1)/WP (IO2)GNDVCC/HOLD or /RESET(IO3)DI (IO0)CLKTop View 8765 Figure 1b. W25Q128JV Pad Assignments, 8-pad WSON 6x5-mm/ 8x6-mm (Package Code P/E) Pin Description SOIC 208-mil, WSON 6x5-mm / 8x6-mm PAD NO. PAD NAME I/O FUNCTION 1 /CS I Chip Select Input 2 DO (IO1) I/O Data Output (Data Input Output 1)(1) 3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)(2) 4 GND Ground 5 DI (IO0) I/O Data Input (Data Input Output 0)(1) 6 CLK I SERIAL Clock Input 7 /HOLD or /RESET (IO3) I/O Hold or Reset Input (Data Input Output 3)(2) 8 VCC Power Supply Notes: 1.