48 x 84 pixels matrix LCD controller/driver

1 INTEGRATED CIRCUITS. DATA SHEET. PCD8544. 48 84 pixels matrix LCD. controller/driver Product specification 1999 Apr 12. File under Integrated Circuits, IC17. Philips Semiconductors Product specification 48 84 pixels matrix LCD controller/driver PCD8544. CONTENTS 8 INSTRUCTIONS. Initialization 1 FEATURES. Reset function 2 GENERAL DESCRIPTION Function set 3 APPLICATIONS Bit PD. Bit V. 4 ORDERING INFORMATION. Bit H. 5 BLOCK DIAGRAM display control 6 PINNING Bits D and E. Pin functions Set Y address of RAM. R0 to R47 row driver outputs Set X address of RAM. C0 to C83 column driver outputs Temperature control VSS1, VSS2: negative power supply rails Bias value VDD1, VDD2: positive power supply rails Set VOP value VLCD1, VLCD2: LCD power supply 9 LIMITING VALUES.

2 T1, T2, T3 and T4: test pads 10 HANDLING. SDIN: serial data line SCLK: serial clock line 11 DC CHARACTERISTICS. D/C: mode select 12 AC CHARACTERISTICS. SCE: chip enable Serial interface OSC: oscillator Reset RES: reset 13 APPLICATION INFORMATION. 7 FUNCTIONAL DESCRIPTION. 14 BONDING PAD LOCATIONS. Oscillator Bonding pad information Address Counter (AC). Bonding pad location display Data RAM (DDRAM). Timing generator 15 TRAY INFORMATION. display address counter 16 DEFINITIONS. LCD row and column drivers 17 LIFE SUPPORT APPLICATIONS. Addressing Data structure Temperature compensation 1999 Apr 12 2. Philips Semiconductors Product specification 48 84 pixels matrix LCD controller/driver PCD8544.

3 1 FEATURES 2 GENERAL DESCRIPTION. Single chip LCD controller/driver The PCD8544 is a low power CMOS LCD controller/driver , 48 row, 84 column outputs designed to drive a graphic display of 48 rows and 84 columns. All necessary functions for the display are display data RAM 48 84 bits provided in a single chip, including on-chip generation of On-chip: LCD supply and bias voltages, resulting in a minimum of Generation of LCD supply voltage (external supply external components and low power consumption. also possible) The PCD8544 interfaces to microcontrollers through a Generation of intermediate LCD bias voltages serial bus interface. Oscillator requires no external components (external The PCD8544 is manufactured in n-well CMOS.)

4 Clock also possible). technology. External RES (reset) input pin Serial interface maximum Mbits/s 3 APPLICATIONS. CMOS compatible inputs Telecommunications equipment. Mux rate: 48. Logic supply voltage range VDD to VSS: to V. display supply voltage range VLCD to VSS. to V with LCD voltage internally generated (voltage generator enabled). to V with LCD voltage externally supplied (voltage generator switched-off). Low power consumption, suitable for battery operated systems Temperature compensation of VLCD. Temperature range: 25 to +70 C. 4 ORDERING INFORMATION. PACKAGE. TYPE NUMBER. NAME DESCRIPTION VERSION. PCD8544U chip with bumps in tray; 168 bonding pads + 4 dummy pads . 1999 Apr 12 3. Philips Semiconductors Product specification 48 84 pixels matrix LCD controller/driver PCD8544.

5 5 BLOCK DIAGRAM. handbook, full pagewidth C1 to C83 R0 to R47. COLUMN DRIVERS ROW DRIVERS. BIAS. VLCD2 VOLTAGE. GENERATOR. DATA LATCHES SHIFT REGISTER. RESET RES. OSCILLATOR OSC. VLCD. VLCD1. GENERATOR display DATA RAM. (DDRAM). TIMING. 48 84. GENERATOR. VDD1 to VDD2. VSS1 to VSS2. display . ADDRESS. T1 ADDRESS COUNTER COUNTER. T2. DATA. T3 PCD8544. REGISTER. T4. I/O BUFFER. MGL629. SDIN SCLK D/C SCE. Block diagram. 1999 Apr 12 4. Philips Semiconductors Product specification 48 84 pixels matrix LCD controller/driver PCD8544. 6 PINNING VLCD1, VLCD2: LCD POWER SUPPLY. SYMBOL DESCRIPTION Positive power supply for the liquid crystal display . Supply rails VLCD1 and VLCD2 must be connected together.

6 R0 to R47 LCD row driver outputs C0 to C83 LCD column driver outputs T1, T2, T3 AND T4: TEST PADS. VSS1, VSS2 ground T1, T3 and T4 must be connected to VSS, T2 is to be left VDD1, VDD2 supply voltage open. Not accessible to user. VLCD1, VLCD2 LCD supply voltage T1 test 1 input SDIN: SERIAL DATA LINE. T2 test 2 output Input for the data line. T3 test 3 input/output T4 test 4 input SCLK: SERIAL CLOCK LINE. SDIN serial data input Input for the clock signal: to Mbits/s. SCLK serial clock input D/C: MODE SELECT. D/C data/command SCE chip enable Input to select either command/address or data input. OSC oscillator SCE: CHIP ENABLE. RES external reset input The enable pin allows data to be clocked in.

7 The signal is dummy1, 2, 3, 4 not connected active LOW. Note 1. For further details, see and Table 7. OSC: OSCILLATOR. When the on-chip oscillator is used, this input must be Pin functions connected to VDD. An external clock signal, if used, is connected to this input. If the oscillator and external clock R0 TO R47 ROW DRIVER OUTPUTS. are both inhibited by connecting the OSC pin to VSS, the These pads output the row signals. display is not clocked and may be left in a DC state. To avoid this, the chip should always be put into C0 TO C83 COLUMN DRIVER OUTPUTS Power-down mode before stopping the clock. These pads output the column signals. RES: RESET. VSS1, VSS2: NEGATIVE POWER SUPPLY RAILS This signal will reset the device and must be applied to properly initialize the chip.

8 The signal is active LOW. Supply rails VSS1 and VSS2 must be connected together. VDD1, VDD2: POSITIVE POWER SUPPLY RAILS. Supply rails VDD1 and VDD2 must be connected together. 1999 Apr 12 5. Philips Semiconductors Product specification 48 84 pixels matrix LCD controller/driver PCD8544. 7 FUNCTIONAL DESCRIPTION Timing generator Oscillator The timing generator produces the various signals required to drive the internal circuits. Internal chip The on-chip oscillator provides the clock signal for the operation is not affected by operations on the data buses. display system. No external components are required and the OSC input must be connected to VDD. An external display address counter clock signal, if used, is connected to this input.

9 The display is generated by continuously shifting rows of Address Counter (AC) RAM data to the dot matrix LCD through the column outputs. The display status (all dots on/off and The address counter assigns addresses to the display normal/inverse video) is set by bits E and D in the display data RAM for writing. The X-address X6 to X0 and the control' command. Y-address Y2 to Y0 are set separately. After a write operation, the address counter is automatically LCD row and column drivers incremented by 1, according to the V flag . The PCD8544 contains 48 row and 84 column drivers, display Data RAM (DDRAM) which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be The DDRAM is a 48 84 bit static RAM which stores the displayed.

10 Figure 2 shows typical waveforms. Unused display data. The RAM is divided into six banks of 84 bytes outputs should be left unconnected. (6 8 84 bits). During RAM access, data is transferred to the RAM through the serial interface. There is a direct correspondence between the X-address and the column output number. 1999 Apr 12 6. Philips Semiconductors Product specification 48 84 pixels matrix LCD controller/driver PCD8544. frame n frame n + 1. VLCD Vstate1(t). V2 Vstate2(t). V3. ROW 0. R0 (t) V4. V5. VSS. VLCD. V2. ROW 1 V3. R1 (t) V4. V5. VSS. VLCD. V2. COL 0 V3. C0 (t) V4. V5. VSS. VLCD. V2. COL 1 V3. C1 (t) V4. V5. VSS. VLCD. V3 - VSS. VLCD - V2 V4 - V5. Vstate1(t) 0V 0V. V3 - V2 VSS - V5.