16-Channel Constant-Current LED Driver

1 A6282 DescriptionThe A6282 device is designed for LED display applications. This CMOS device includes an input shift register, accompanying data latches, and 16 MOS constant current sink CMOS shift registers and latches allow direct interfacing with microprocessor-based systems. With a or 5 V logic supply, typical serial data input rates can reach up to 30 MHz. The LED drive current level can be set by a single external resistor, selected by the application designer. A serial data output permits cascading of multiple devices in applications requiring additional drive A6282 is available in two 24-terminal packages: QFN (package ES) and TSSOP (LP), which have an exposedthermal pad. Both packages are lead (Pb) free with 100% matte tin leadframe include the following: Monocolor, multicolor, or full-color LED display Monocolor, multicolor, or full-color LED signboard Display backlighting Multicolor LED lighting6282-DS, Rev.

2 4 Features and Benefits 16 Constant-Current outputs, up to 50 mA each LED output voltage up to 12 V to V logic supply range Schmitt trigger inputs for improved noise immunity Power-On Reset (POR), all register bits = 0 Low-power CMOS logic and latches High data input rate: 30 MHz Output current accuracy: between channels < 3% and between ICs 7%, over the full operating temperature range Internal UVLO and thermal shutdown (TSD) circuitry16-Channel Constant-Current LED DriverTypical ApplicationControllerCLKLESDOREXTA6282IC 1A6282IC 2 OESDISDI10 F100 nFOUT0 OUT15 VLEDVDDCLKLEOECLKLEOEREXT100 nFVDD10 FOUT0 OUT15 SDOSDIGNDGNDVDDVDDNot to scale24-contact QFN4 mm 4 mm mm(Package ES)24-pin TSSOP with exposed thermal pad(Package LP)Cascaded A6282 devicesPackages: 16-Channel Constant-Current LED DriverA62822 Allegro MicroSystems, Northeast CutoffWorcester, Massachusetts 01615-0036 ; Maximum RatingsCharacteristicSymbolNotesRatingUn itSupply Voltage*VDD to OUTx current (any single output)IO60mA Input Voltage Range*VI VOE, VLE, VCLK, VSDI to VDD + LED Load Supply Range*VLED to ESD Rating HBM (JEDEC JESD22-A114, Human Body Model) CDM (JEDEC JESD22-C101, Charged Device Model) Operating Temperature Range (E)TA 40 to 85 CJunction TemperatureTJ(max)150 CStorage Temperature Range Tstg 55 to 150 C *With respect to GuidePart NumberPackagePackingA6282 EESTR-T4 mm 4 mm QFN, 24 pins, exposed thermal pad1500 pieces per 7-in.

3 ReelA6282 ELPTR-TTSSOP, 24 pins, exposed thermal pad4000 pieces per 13 in. reelThermal CharacteristicsCharacteristicSymbolTest Conditions1 ValueUnitsPackage Thermal ResistanceR JAES package, 4-layer PCB based on JEDEC standard37 C/WLP packge, 4-layer PCB based on JEDEC standard28 C/W*Additional thermal information available on the Allegro Package Power Dissipation (W)Ambient Temperature ( C) LP, RQJA = 28 C/WPackage ES, RQJA = 37 C/W16-Channel Constant-Current LED DriverA62823 Allegro MicroSystems, Northeast CutoffWorcester, Massachusetts 01615-0036 ; Block DiagramInputs and Outputs Equivalent CircuitsResistor values are equivalent resistance and not testedVDDCLK, SDI,LE, O E 500 SDOVDD10 SDO SDILEOUT0 OUT1 OUT15 UVLO and TSDVDDIOR egulatorREXTS erial - Parallel Shift RegisterControl Logic BlockCLKO utput Control drivers VLEDE xposed Pad(ET and LP packages)OEGNDL atches16-Channel Constant-Current LED DriverA62824 Allegro MicroSystems, Northeast CutoffWorcester, Massachusetts 01615-0036 ; List TableNameNumberDescriptionESLPCLK 63 Clock; data shift clock input terminalGND41 Logic supply ground and load supply groundLE 74 Latch Enable input terminal O E 2421 Output Enable input terminal, active low (when O E = high, all OUTx outputs are forced off.)

4 When O E = low, on/off status of OUTx outputs is controlled by the state of the latchesOUT0 85 constant current outputsOUT1 96 OUT2 107 OUT3 118 OUT4 129 OUT5 1310 OUT6 1411 OUT7 1512 OUT8 1613 OUT9 1714 OUT10 1815 OUT11 1916 OUT12 2017 OUT13 2118 OUT14 2219 OUT15 2320 PAD Exposed pad for enhanced thermal dissipation; not connected internally, connect to GNDREXT 223 Reference current terminal; sets output current for all channelsSDI52 Serial Data In terminalSDO 122 Serial Data Out terminalVDD324 Logic Supply terminalPin-out DiagramsTop-down views12345678910111224232221201918171615 1413 VDDREXTSDOOEOUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 PADGNDSDICLKLEOUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 PAD1817161514131234567891011122423222120 19 OEOUT15 OUT14 OUT13 OUT12 OUT11 LEOUT0 OUT1 OUT2 OUT3 OUT4 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 SDOREXTVDDGNDSDICLKES PackageLP Package16-Channel Constant-Current LED DriverA62825 Allegro MicroSystems, Northeast CutoffWorcester, Massachusetts 01615-0036.

5 CHARACTERISTICS at TA1 = 25 C, VDD = to V, unless otherwise notedCharacteristicSymbolTest Supply Voltage Load Supply Output VoltageVLEDO perating LockoutVDD(UV)VDD 0 5 CurrentIOVDD = to V, VDS(x) = 1 V, REXT = 374 = to V, VDS(x) = 1 V, REXT = 374 = to V, VDS(x) = 1 V,REXT = 910 = to V, VDS(x) = 1 V, REXT = 910 current Shift% IOVDD = V, VDS(x) = 1 V, REXT = 910 , TA = 25 C; between one output on and all outputs on 1%Output to Output Matching Error3 ErrVDS = 1 V, REXT = 374 , all outputs on + + = 1 V, REXT = 910 , all outputs on + + current Regulation%IO(reg)VDD = V, VDS(x) = 1 to 3 V, REXT = 374 , all outputs on = V, VDS(x) = 1 to 3 V, REXT = 910 , all outputs on = V, VDS(x) = 1 to 3 V, REXT = 374 , all outputs on = V, VDS(x) = 1 to 3 V, REXT = 910 , all outputs on Leakage CurrentIDSSVOH = 12 V ALogic Input VDD VDDVVILGND VDDVL ogic Input Voltage HysteresisVIhysAll digital inputs250 900mVLogic Input CurrentIIAll digital inputs 1 1 ASDO VoltageVOLIOL = 1 mA = 1 mAVDD VSupply Current4 IDD(OFF)REXT = k , VOE = 5 V 6mAREXT = 910 , VOE = 5 V 16mAREXT = 374 , VOE = 5 V 40mAIDD(ON)

6 All outputs on, REXT = 910 , VO = 1 V,data transfer 30 MHz 20mAAll outputs on, REXT = 374 , VO = 1 V,data transfer 30 MHz 45mAContinued on the next Constant-Current LED DriverA62826 Allegro MicroSystems, Northeast CutoffWorcester, Massachusetts 01615-0036 ; CHARACTERISTICS (continued), at TA1 = 25 C, VDD = to V, unless otherwise notedCharacteristicSymbolTest CHARACTERISTICS at TA1 = 25 C, VDD = VIH = V, VDS = 1 V, VIL = 0 V, REXT = 910 , IO = mA, VL = 2 V, RL = 51 , CL = 15 pF (see also Timing Diagrams section)CharacteristicSymbolTest FrequencyfCLKCLK 30 MHz Clock Frequency (cascaded devices)fCLKCCLK 25 MHz Clock Pulse Durationtwh0 CLK = high16 ns LE Pulse Duration twh1LE = high20 ns Setup Timetsu0 SDI to CLK 10 ns tsu1 CLK to LE 10 ns Hold Time th0 CLK to SDI10 ns th1LE to CLK 10 ns Rise Timetr0 SDO, 10/90% points (measurement circuit A) 16nstr1 OUTx, VDD = 5 V,10/90% points (measurement circuit B) 1030nsFall Time tf0 SDO, 10/90% points (measurement circuit A) 16nstf1 OUTx, VDD = 5 V,10/90% points (measurement circuit B) 1030nsPropagation Delay Time tpd0 CLK to SDO (measurement circuit A) 30nstpd1 O E to OUTx (measurement circuit B)

7 60nstpd2LE to OUTx (measurement circuit B) 60nsOutput Enable Pulse Durationtw(OE) (see Timing Diagrams section)60 ns1 Tested at 25 C. Specifications are assured by design and characterization over the operating temperature range of 40 C to 85 data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum Shutdown TemperatureTJTSDT emperature increasing 165 CThermal Shutdown HysteresisTJTSDhys 15 CReference Voltage at External Resistor REXTVEXTREXT = 374 V1 Tested at 25 C. Specifications are assured by design and characterization over the operating temperature range of 40 C to 85 data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum = (IO(min or max) IO(av)) / IO(av).

8 IO(av) is the average current of all outputs. IO(min or max) is the output current with the greatest difference from IO(av).4 Recommended operating range: VO = to pFOUTxA6282 RLVLCLA6282 Parameter Measurement Circuits(A) Circuit for tf0 , tpd0 , and tr0(B) Circuit for tf1 , tpd1 , tpd2 , and tr1 . 16-Channel Constant-Current LED DriverA62827 Allegro MicroSystems, Northeast CutoffWorcester, Massachusetts 01615-0036 ; ( current )pd2tOELow = All Outputs EnabledHigh = Output onLow = Output offOUTx( current )OEpd1tpd1t50%50%50%r0tf0 t10%90%f1tr1t90%10%50% w (OE)tTiming DiagramsDisabling OutputsNormal Operation16-Channel Constant-Current LED DriverA62828 Allegro MicroSystems, Northeast CutoffWorcester, Massachusetts 01615-0036 ; CharacteristicsREXT = 470 REXT = 910 (V)IO(max) (mA)IO (mA)REXT (k ) VDD (V) to to Maximum constant Output current versus External Reference ResistanceInput-Output Truth TableSerial Data Input(SDI)Clock Input(CLK)Shift Register ContentsSerial Data Out(SDO)Latch Enable Input(LE)Latch ContentsOutput Enable Input( O E )Output Contents I0 I1 I2.

9 I15 I0 I1 I2 .. I15 I0 I1 I2 .. I15H H R0 R1 .. R15R14 L L R0 R1 .. R15R14X R0 R1 R2 .. R15R15 X X X .. XXL R0 R1 R2 .. R15 P0 P1 P2 .. P15P15H P0 P1 P2 .. P15L(Outputs on) P0 P1 P2 .. P15 X X X .. XH(Outputs off) H H H .. HL = Low logic (voltage) level, H = High logic (voltage) level, X = Don t care, P = Present state, R = Previous stateChannel Output current versus Output VoltageVDD = V16-Channel Constant-Current LED DriverA62829 Allegro MicroSystems, Northeast CutoffWorcester, Massachusetts 01615-0036 ; OperationSerial data present at the SDI (Serial Data In) input is transferred to the shift register on the transition from logic 0 to logic 1 of the CLK (Clock) input pulse. On succeeding CLK pulses, the register shifts data towards the SDO (Serial Data Out) output. The serial data must appear at the input prior to the rising edge of the CLK waveform.

10 Data present in any register is transferred to the respective latch when the LE (Latch Enable) input is high (serial-to-parallel con-version). The latches continue to accept new data as long as LE is held high (level triggered). Applications where the latches are bypassed (LE tied high) require that the O E (Output Enable) input be high during serial data entry. When O E is high, the output sink drivers are disabled (off). The data stored in the latches is not affected by the state of O E . With O E active (low), the outputs are controlled by the state of their respective Maximum Channel CurrentThe maximum output current per channel is set by a single exter-nal resistor, REXT, which is placed between the REXT pin and GND. The voltage on REXT, VEXT, is set by an internal band gap and is V, typical. The maximum channel output current can be calculated as: IO(max) = ( REXT) + , for VDD = to V , or IO(max) = ( REXT) + , for VDD = to V ,where REXT is the value of the user-selected external resistor, which should not be less than 374.