7 Series FPGAs Configurable Logic Block User Guide (UG474)

1 7 Series FPGAs Configurable Logic BlockUser GuideUG474 ( ) September 27, 20167 Series FPGAs CLB user ( ) September 27, 2016 DISCLAIMERThe information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available AS IS and with all faults, xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or xilinx had been advised of the possibility of the same.

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3 CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. Copyright 2011 2016 xilinx , Inc. xilinx , the xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of xilinx in the United States and other countries. All other trademarks are the property of their respective HistoryThe following table shows the revision history for this Initial devices XC7K355T, XC7K420T, and XC7K480T to Table 1-3. Portions of the text have been revised for last sentence under 7 Series CLB Features. Added Table 1-3 and Table 1-4. Updated CLB features in Table 1-3. Added first sentence under CLB Arrangement, added ASMBL Architecture section, and CLB Slices heading.

4 Added last paragraph under Carry Logic . Added lasts sentence under Using Carry Logic . Added second sentence under Slice Multiplexer Timing Parameters. Modified Table 5-2, Table 5-4, and Table 5-5 for clarity. Added Devices Using Stacked Silicon Interconnect (SSI) Technology Table 1-2. Added fifth paragraph under Distributed RAM (Available in SLICEM Only). Clarified last paragraph under Global Controls GSR and uniformity to optimized in last bullet under 7 Series CLB Features. Changed unified to scalable in first sentence under Device Resources. Deleted 7A350T device from Table 1-2. Deleted 7V1500T and 7VH290T devices from Table 1-4. Added reference to 7 Series FPGA Libraries Guide to Distributed RAM (Available in SLICEM Only), Shift Registers (Available in SLICEM Only), and Flip-Flop Primitives. Changed TCEO to TCECK in Figure 5-2 and first bullet under General Timing ( ) September 27, Series FPGAs CLB user Guide08/6 Artix -7 devices.

5 Updated references to implementation Revised footnotes in Table 1-2 through Table 1-4. Revised polarity from independent to programmable in Control Signals, page 22. Added Primitive column to Table 2-3 and removed footnotes. Renamed or made minor revisions to Figure 2-6 through Figure 2-14. Revised sections Clock WCLK, page 49, Clock CLK, page 50, and Clock - C, page Updated Table 1-2 for new Artix 7A15T Spartan -7 device family (updated Preface and added Table 1-1). Added Artix -7 7A12T and 7A25T devices to Table Series FPGAs CLB user ( ) September 27, 20167 Series FPGAs CLB user ( ) September 27, 2016 Revision History .. 2 Preface: About This GuideGuide Contents .. 7 Additional Support Resources.. 8 Chapter 1: OverviewCLB Overview .. 97 Series CLB Features .. 10 Device Resources .. 10 Recommended Design Flow.

6 12 Pinout Planning.. 13 Chapter 2: Functional DetailsCLB Arrangement.. 15 Slice Description.. 18 Look-Up Table (LUT) .. 21 Storage Elements.. 21 Distributed RAM (Available in SLICEM Only) .. 23 Shift Registers (Available in SLICEM Only).. 34 Multiplexers .. 39 Carry Logic .. 43 Chapter 3: Design EntryDesign Checklist.. 45 Using the CLB Resources.. 46 Primitives.. 46 Chapter 4: ApplicationsDistributed RAM Applications.. 53 Shift Register Applications.. 53 Carry Logic Applications.. 55 Chapter 5: TimingCLB General Slice Timing Model and Parameters.. 58 CLB Slice Multiplexer Timing Model and Parameters.. 60 CLB Slice Carry-Chain Timing Model and Parameters .. 61 Table of ContentsSend Series FPGAs CLB user GuideUG474 ( ) September 27, 2016 CLB Slice Distributed RAM Timing Model and Parameters (Available in SLICEM Only) 63 CLB Slice SRL Shift Register Timing Model and Parameters (Available in SLICEM Only).

7 66 Chapter 6: Advanced TopicsUsing the Latch Function as Logic .. 71 Interconnect Resources.. 72 Devices Using Stacked Silicon Interconnect (SSI) Technology .. 73 Send Feedback7 Series FPGAs CLB user ( ) September 27, 2016 PrefaceAbout This GuideXilinx 7 Series FPGAs include four FPGA families that are all designed for lowest power to enable a common design to scale across families for optimal power, performance, and cost. The Spartan -7 family is the lowest density with the lowest cost entry point into the 7 Series portfolio. The Artix -7 family is optimized for highest performance-per-watt and bandwidth-per-watt for cost-sensitive, high-volume applications. The Kintex -7 family is an innovative class of FPGAs optimized for the best price-performance. The Virtex -7 family is optimized for highest system performance and capacity. This Guide serves as a technical reference describing the 7 Series FPGAs Configurable Logic blocks (CLBs).

8 Usually, Logic synthesis assigns the CLB resources without system designer intervention. It can be advantageous for the designer to understand certain CLB details, including the varying capabilities of the look-up tables (LUTs), the physical direction of the carry propagation, the number and distribution of the available flip-flops, and the availability of the very efficient shift registers. This Guide describes these and other features of the CLB in 7 Series FPGAs Configurable Logic Block user Guide , part of an overall set of documentation on the 7 Series FPGAs , is available on the ContentsThis manual contains these chapters: Chapter 1, Overview, provides basic information needed for the majority of users, including: CLB Overview is targeted at the new user . 7 Series CLB Features discusses what is new compared with the Spartan -6 and Virtex -6 FPGA families for the experienced user and provides design migration considerations.

9 Device Resources indicates the number of resources per device, and unity between different 7 Series families. Recommended Design Flow provides the basics of using CLB resources and lists key aspects to consider. Pinout Planning discusses aspects of CLBs that might affect pin placement for a design. Chapter 2, Functional Details, lists architectural specifics for each CLB feature. Chapter 3, Design Entry, provides design entry guidelines and primitives for instantiation. Chapter 4, Applications, provides examples that use the CLB resources in larger Series FPGAs CLB user GuideUG474 ( ) September 27, 2016 Preface:About This Guide Chapter 5, Timing, contains timing models and defines CLB timing specifications from the respective 7 Series FPGA data sheet. Chapter 6, Advanced Topics, discusses advanced features of the 7 Series Support ResourcesTo find additional documentation, see the xilinx website at: #documentationTo search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the xilinx website Feedback7 Series FPGAs CLB user ( ) September 27, 2016 Chapter 1 OverviewCLB OverviewThe 7 Series Configurable Logic Block (CLB) provides advanced, high-performance FPGA Logic : Real 6-input look-up table (LUT) technology Dual LUT5 (5-input LUT) option Distributed Memory and Shift Register Logic capability Dedicated high-speed carry Logic for arithmetic functions Wide multiplexers for efficient utilizationCLBs are the main Logic resources for implementing sequential as well as combinatorial circuits.

10 Each CLB element is connected to a switch matrix for access to the general routing matrix (shown in Figure 1-1). A CLB element contains a pair of LUTs in 7 Series FPGAs can be configured as either a 6-input LUT with one output, or as two 5-input LUTs with separate outputs but common addresses or Logic inputs. Each 5-input LUT output can optionally be registered in a flip-flop. Four such 6-input LUTs and their eight flip-flops as well as multiplexers and arithmetic carry Logic form a slice, and two slices form a CLB. Four flip-flops per slice (one per LUT) can optionally be configured as latches. In that case, the remaining four flip-flops in that slice must remain Target - Figure 1-1 Figure 1-1:Arrangement of Slices within the CLBS witchMatrixSlice(1)COUTCOUTCINCINS lice(0)CLBUG474_c1_01_071910 Send Series FPGAs CLB user GuideUG474 ( ) September 27, 2016 Chapter 1:OverviewApproximately two-thirds of the slices are SLICEL Logic slices and the rest are SLICEM, which can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two SRL16s.