7 Series FPGAs Integrated Block for PCI Express v3

1 7 Series FPGAs Integrated Block for PCI Express LogiCORE IP Product GuideVivado Design SuitePG054 November 19, 2014 7 Series Integrated Block for PCIe November 19, 2014 Table of ContentsIP FactsChapter 1: OverviewFeature Summary.. 5 Applications .. 6 Licensing and Ordering Information .. 6 Chapter 2: Product SpecificationStandards Compliance .. 8 Resource Utilization .. 9 Minimum Device Requirements .. 10 Available Integrated Blocks for PCIe.. 11 Core Interfaces .. 12 Transaction Interface .. 15 PCI Configuration Space .. 39 Chapter 3: Designing with the CoreGeneral Design Guidelines.

2 45 Tandem Configuration .. 153 Clocking.. 181 Resets .. 184 Protocol Layers.. 185 Shared Logic .. 187 FPGA Configuration .. 194 Chapter 4: Design Flow StepsCustomizing and Generating the Core .. 203 Constraining the Core .. 239 Simulation .. 254 Synthesis and Implementation .. 257 Chapter 5: Detailed Example DesignsIntegrated Block Endpoint Configuration Overview .. 258 Send Feedback7 Series Integrated Block for PCIe November 19, 2014 Programmed Input/Output: Endpoint Example Design .. 261 Configurator Example Design .. 275 Generating the Core.

3 281 Simulating the Example Design.. 284 Synthesizing and Implementing the Example Design .. 285 Directory and File Contents .. 286 Chapter 6: Test BenchesRoot Port Model Test Bench for Endpoint .. 296 Endpoint Model Test Bench for Root Port .. 308 Appendix A: Migrating and UpgradingMigrating to the Vivado Design Suite .. 311 Upgrading in the Vivado Design Suite .. 322 Appendix B: DebuggingFinding Help on .. 325 Debug Tools .. 327 Simulation Debug.. 330 Hardware Debug .. 333 Appendix C: Managing Receive-Buffer Space for Inbound CompletionsGeneral Considerations and Concepts.

4 347 Methods of Managing Completion Space .. 348 Appendix D: PCIE_2_1 Port DescriptionsClock and Reset Interface .. 354 Transaction Layer Interface .. 355 Block RAM Interface .. 359 GTX Transceiver Interface .. 360 Configuration Management Interface .. 367 Dynamic Reconfiguration Port Interface .. 392TL2 Interface Ports .. 393 Appendix E: Additional Resources and Legal NoticesXilinx Resources .. 395 References .. 395 Revision History .. 396 Please Read: Important Legal Notices .. 397 Send Feedback7 Series Integrated Block for PCIe November 19, 2014 Product SpecificationIntroductionThe 7 Series FPGAs Integrated Block for PCI Express core is a scalable, high-bandwidth, and reliable serial interconnect building Block for use with xilinx Zynq -7000 All Programmable SoC, and 7 Series FPGA families.

5 The 7 Series Integrated Block for PCI Express (PCIe ) solution supports 1-lane, 2-lane, 4-lane, and 8-lane Endpoint and Root Port configurations at up to 5 Gb/s (Gen2) speeds, all of which are compliant with the PCI Express Base Specification, rev. This solution supports the AMBA AXI4-Stream interface for the customer user higher bandwidth per pin, low overhead, low latency, reduced signal integrity issues, and CDR architecture, the 7 Series Integrated Block for PCIe sets the industry standard for a high-performance, cost-efficient, third-generation I/O High-performance, highly flexible, scalable, and reliable.

6 General-purpose I/O core Incorporates xilinx Smart-IP technology to guarantee critical timing Uses GTXE2 or GTPE2 transceivers for 7 Series FPGA families GT/s and GT/s line speeds Supports 1-lane, 2-lane, 4-lane, and 8-lane operation Elastic buffers and clock compensation Automatic clock data recovery Supports Endpoint and Root Port configurations 8B/10B encode and decode Supports Lane Reversal and Lane Polarity Inversion per PCI Express specification requirements Standardized user interface Compliant with PCI/PCI Express power management functions, and transaction ordering rules Supports a maximum transaction payload of up to 1024 bytes Supports Multi-Vector MSI for up to 32 vectors and MSI-X Up-configure capability enables application driven bandwidth scalabilityIP FactsLogiCORE IP Facts TableCore SpecificsSupported Device Family(1)Zynq-7000, Virtex -7, Kintex -7, Artix -7 Supported User InterfacesAXI4-StreamResourcesSee Ta b l e 2 - with CoreDesign FilesVerilog/VHDL(2)

7 RTL Sourceand Simulation ModelsExample DesignVerilog, VHDLTest BenchVerilog, VHDLC onstraints FileXDCS imulation ModelVerilog, VHDLS upported S/W DriverN/ATested Design Flows(3)Design EntryVivado Design SuiteVivadoSimulationFor a list of supported simulators, see theXilinx Design Tools: Release Notes GuideSynthesisVivado SynthesisSupportProvided by xilinx @ : 1. For a complete listing of supported devices, see the Vivado IP RTL source for the GTX wrapper is Verilog only. VHDL projects require mixed language mode simulators. 3. For the supported versions of the tools, see theXilinx Design Tools: Release Notes Feedback7 Series Integrated Block for PCIe November 19, 2014 Chapter 1 OverviewXilinx 7 Series FPGAs include three unified FPGA families that are all designed for lowest power to enable a common design to scale across families for optimal power, performance, and cost.

8 The Artix -7 family is optimized for lowest cost and absolute power for the highest volume applications. The Virtex -7 family is optimized for highest system performance and capacity. The Kintex -7 family is an innovative class of FPGAs optimized for the best price to performance. This document describes the function and operation of the 7 Series FPGAs Integrated Block for PCI Express , including how to design, customize, and implement it. The 7 Series FPGAs Integrated Block for PCI Express core is a reliable, high-bandwidth, scalable serial interconnect building Block .

9 The core instantiates the 7 Series Integrated Block for PCI Express found in the 7 Series FPGAs , and supports both Verilog and VHDL. This core simplifies the design process and reduces time to market. It is configurable for Endpoint and Root Port applications. This solution can be used in communication, multimedia, server and mobile platforms and enables applications such as high-end medical imaging, graphics intensive video games, DVD quality streaming video on the desktop, and 10 Gigabit Ethernet interface cards. Although the core is a fully verified solution, the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application.

10 RECOMMENDED:For the best results, previous experience building high-performance, pipelined FPGA designs using xilinx implementation software and constraints files is SummaryThe 7 Series Integrated Block for PCIe follows the PCI Express Base Specification, rev. [Ref 2] layering model, which consists of the Physical, Data Link, and Transaction Layers. The protocol uses packets to exchange information between layers. Packets are formed in the Transaction and Data Link Layers to carry information from the transmitting component to the receiving component. Necessary information is added to the packet being transmitted, which is required to handle the packet at specific layers.