8259A PROGRAMMABLE INTERRUPT CONTROLLER …

1 December 1988 Order Number: 231468-0038259 APROGRAMMABLE INTERRUPT CONTROLLER ( 8259A / 8259A -2)Y8086, 8088 CompatibleYMCS-80, MCS-85 CompatibleYEight-Level Priority ControllerYExpandable to 64 LevelsYProgrammable INTERRUPT ModesYIndividual Request Mask CapabilityYSinglea5V Supply (No Clocks)YAvailable in 28-Pin DIP and 28-LeadPLCC Package(See Packaging Spec., Order 231369)YAvailable in EXPRESS Standard Temperature Range Extended Temperature RangeThe Intel 8259A PROGRAMMABLE INTERRUPT CONTROLLER handles up to eight vectored priority interrupts for the is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pinDIP, uses NMOS technology and requires a singlea5V supply. Circuitry is static, requiring no clock 8259A is designed to minimize the software and real time overhead in handling multi-level priority inter-rupts.

2 It has several modes, permitting optimization for a variety of system 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will operatethe 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).231468 1 Figure 1. Block DiagramDIP231468 2 PLCC231468 31 Figure 2. PinConfigurations8259 ATable 1. Pin DescriptionSymbolPin No. TypeName and FunctionVCC28 ISUPPLY:a5V SELECT:A low on this pin enables RDand WRcommunicationbetween the CPU and the 8259A . INTA functions are independent :A low on this pin when CS is low enables the 8259A to acceptcommand words from the :A low on this pin when CS is low enables the 8259A to releasestatus onto the data bus for the D04 11I/OBIDIRECTIONAL DATA BUS:Control, status and INTERRUPT -vectorinformation is transferred via this CAS212, 13, 15 I/OCASCADE LINES:The CAS lines form a private 8259A bus to controla multiple 8259A structure.

3 These pins are outputs for a master 8259 Aand inputs for a slave PROGRAM/ENABLE BUFFER:This is a dual function in the Buffered Mode it can be used as an output to controlbuffer transceivers (EN). When not in the buffered mode it is used asan input to designate a master (SPe1) or slave (SPe0).INT17 OINTERRUPT:This pin goes high whenever a valid INTERRUPT request isasserted. It is used to INTERRUPT the CPU, thus it is connected to theCPU s INTERRUPT IR718 25 IINTERRUPT REQUESTS:Asynchronous inputs. An INTERRUPT requestis executed by raising an IR input (low to high), and holding it high untilit is acknowledged (Edge Triggered Mode), or just by a high level on anIR input (Level Triggered Mode).INTA26 IINTERRUPT ACKNOWLEDGE:This pin is used to enable 8259 Ainterrupt-vector data onto the data bus by a sequence of interruptacknowledge pulses issued by the ADDRESS LINE:This pin acts in conjunction with the CS,WR, andRDpins.

4 It is used by the 8259A to decipher various Command Wordsthe CPU writes and status the CPU wishes to read. It is typicallyconnected to the CPU A0 address line (A1 for 8086, 8088).28259 AFUNCTIONAL DESCRIPTIONI nterrupts in Microcomputer SystemsMicrocomputer system design requires that de-vices such as keyboards, displays, sensors and oth-er components receive servicing in a an efficientmanner so that large amounts of the total systemtasks can be assumed by the microcomputer withlittle or no effect on most common method of servicing such devic-es is thePolledapproach. This is where the proces-sor must test each device in sequence and in effect ask each one if it needs servicing. It is easy to seethat a large portion of the main program is loopingthrough this continuous polling cycle and that such amethod would have a serious detrimental effect onsystem throughput, thus limiting the tasks that couldbe assumed by the microcomputer and reducing thecost effectiveness of using such more desirable method would be one that wouldallow the microprocessor to be executing its mainprogram and only stop to service peripheral deviceswhen it is told to do so by the device itself.

5 In effect,the method would provide an external asynchronousinput that would inform the processor that it shouldcomplete whatever instruction that is currently beingexecuted and fetch a new routine that will servicethe requesting device. Once this servicing is com-plete, however, the processor would resume exactlywhere it left method is calledInterrupt. It is easy to see thatsystem throughput would drastically increase, andthus more tasks could be assumed by the micro-computer to further enhance its cost PROGRAMMABLE INTERRUPT CONTROLLER (PIC) func-tions as an overall manager in an INTERRUPT -Drivensystem environment. It accepts requests from theperipheral equipment, determines which of the in-coming requests is of the highest importance (priori-ty), ascertains whether the incoming request has ahigher priority value than the level currently beingserviced, and issues an INTERRUPT to the CPU basedon this peripheral device or structure usually has aspecial program or routine that is associated withits specific functional or operational requirements;this is referred to as a service routine.

6 The PIC,after issuing an INTERRUPT to the CPU, must somehowinput information into the CPU that can point theProgram Counter to the service routine associatedwith the requesting device. This pointer is an ad-dress in a vectoring table and will often be referredto, in this document, as vectoring 3 Figure 3a. Polled Method231468 4 Figure 3b. INTERRUPT Method38259 AThe 8259A is a device specifically designed for usein real time, INTERRUPT driven microcomputer manages eight levels or requests and has built-infeatures for expandability to other 8259A s (up to 64levels). It is programmed by the system s softwareas an I/O peripheral. A selection of priority modes isavailable to the programmer so that the manner inwhich the requests are processed by the 8259A canbe configured to match his system priority modes can be changed or reconfigureddynamically at any time during the main means that the complete INTERRUPT structure canbe defined as required, based on the total REQUEST REGISTER (IRR) ANDIN-SERVICE REGISTER (ISR)The interrupts at the IR input lines are handled bytwo registers in cascade, the INTERRUPT Request Reg-ister (IRR) and the In-Service (ISR).

7 The IRR is usedto store all the INTERRUPT levels which are requestingservice; and the ISR is used to store all the interruptlevels which are being RESOLVERThis logic block determines the priorites of the bitsset in the IRR. The highest priority is selected andstrobed into the corresponding bit of the ISR MASK REGISTER (IMR)The IMR stores the bits which mask the interruptlines to be masked. The IMR operates on the of a higher priority input will not affect theinterrupt request lines of lower ( INTERRUPT )This output goes directly to the CPU INTERRUPT VOHlevel on this line is designed to be fullycompatible with the 8080A, 8085A and 8086 ( INTERRUPT ACKNOWLEDGE)INTA pulses will cause the 8259A to release vector-ing information onto the data bus. The format of thisdata depends on the system mode (mPM) of BUS BUFFERThis 3-state, bidirectional 8-bit buffer is used to inter-face the 8259A to the system Data Bus.

8 Controlwords and status information are transferredthrough the Data Bus CONTROL LOGICThe function of this block is to accept OUTput com-mands from the CPU. It contains the InitializationCommand Word (ICW) registers and OperationCommand Word (OCW) registers which store thevarious control formats for device operation. Thisfunction block also allows the status of the 8259A tobe transferred onto the Data (CHIP SELECT)A LOW on this input enables the 8259A . No readingor writing of the chip will occur unless the device (WRITE)A LOW on this input enables the CPU to write con-trol words (ICWs and OCWs) to the (READ)A LOW on this input enables the 8259A to send thestatus of the INTERRUPT Request Register (IRR), InService Register (ISR), the INTERRUPT Mask Register(IMR), or the INTERRUPT level onto the Data input signal is used in conjunction with WRandRDsignals to write commands into the various com-mand registers, as well as reading the various statusregisters of the chip.

9 This line can be tied directly toone of the address 5 Figure 4a. 8259A Block Diagram58259A231468 6 Figure 4b. 8259A Block Diagram68259 ATHE CASCADE BUFFER/COMPARATORThis function block stores and compares the IDs ofall 8259A s used in the system. The associatedthree I/O pins (CAS0-2) are outputs when the 8259 Ais used as a master and are inputs when the 8259 Ais used as a slave. As a master, the 8259A sendsthe ID of the interrupting slave device onto theCAS0 2 lines. The slave thus selected will send itspreprogrammed subroutine address onto the DataBus during the next one or two consecutive INTA pulses. (See section Cascading the 8259A .) INTERRUPT SEQUENCEThe powerful features of the 8259A in a microcom-puter system are its programmability and the inter-rupt routine addressing capability. The latter allowsdirect or indirect jumping to the specific INTERRUPT rou-tine requested without any polling of the interruptingdevices.

10 The normal sequence of events during aninterrupt depends on the type of CPU being events occur as follows in an MCS-80/85 sys-tem:1. One or more of the INTERRUPT REQUEST lines(IR7 0) are raised high, setting the correspond-ing IRR bit(s).2. The 8259A evaluates these requests, and sendsan INT to the CPU, if The CPU acknowledges the INT and respondswith an Upon receiving an INTA from the CPU group, thehighest priority ISR bit is set, and the correspond-ing IRR bit is reset. The 8259A will also release aCALL instruction code (11001101) onto the 8-bitData Bus through its D7 0 This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the These two INTA pulses allow the 8259A to re-lease its preprogrammed subroutine addressonto the Data Bus. The lower 8-bit address is re-leased at the first INTA pulse and the higher 8-bitaddress is released at the second This completes the 3-byte CALL instruction re-leased by the 8259A .