A Hardware Designer's Informal Guide to Xilinx® Zynq ...

1 A Hardware Designer's Informal Guide to Xilinx zynq UltraScale+ By Fidus Systems For Anyone Interested in Learning More Version: 2020-04-06 Confidential 2 A Hardware Designer's Informal Guide to zynq UltraScale+ Version: 2020-04-06 Revision History Revision Author Release Date Description of Change ST 2020-03-27 Initial Draft (incomplete) ST 2020-04-01 Initial Draft (complete, ready for review) ST 2020-04-06 Updated following review. Released. Confidential 3 A Hardware Designer's Informal Guide to zynq UltraScale+ Version: 2020-04-06 Table of Contents 1 Introduction.

2 5 2 The Tips .. 6 Selecting your Device .. 6 MIO Structure and Function Assignment .. 8 PS MIO Bank Voltage .. 12 Extended Multiplexed IO (EMIO) .. 12 Bank 503 .. 13 Other Dedicated Pins .. 14 PS and PL system Monitor .. 15 PS Transceivers (GTRs) .. 16 PCIe .. 18 Powering the zynq US+ .. 19 Thermals .. 21 Device Configuration .. 22 PL HP and HD .. 23 PS and PL DDR .. 23 PL Transceivers .. 25 Clocks .. 26 PS Clocks .. 26 PL Global Clocks .. 27 XTP427 Schematic Checklist .. 27 3 Debug Peripherals Every zynq US+ Design Should.

3 27 Reset Switches .. 27 Status LEDs .. 27 Debug Headers .. 28 Boot Mode Configuration .. 28 Spare Clocks .. 28 SecureDigital .. 28 4 Typical zynq UltraScale+ Applications .. 29 Video Streaming .. 29 Compute Offload and Acceleration .. 30 Storage .. 31 Confidential 4 A Hardware Designer's Informal Guide to zynq UltraScale+ Version: 2020-04-06 5 About Fidus Systems .. 34 6 References .. 35 General zynq US+ References .. 35 Disclaimer This article is provided for the User s enjoyment.

4 All information contained herein is believed to be correct. It is possible that some information is incorrect, misleading, or out-dated. We recommend that the information contained herein be used as a Guide only, and that the User reviews all claims, concerns, or design decisions, with Xilinx, Xilinx s official information, and/or Xilinx s representatives ( Avnet). Fidus cannot be held responsible for losses or damages associated with the use or misuse of the information within article. Use of this article and the information contained is at User s own risk.

5 The views and opinions expressed in this article are those of the author(s) and do not necessarily reflect the official policy or position of Fidus Systems. Fidus Systems assumes no responsibility or liability for any errors or omissions in the content of this article. The information contained in this article is provided on an "as is" basis with no guarantees of completeness, accuracy, usefulness or timeliness. Fidus Systems is a Xilinx Premier Design Services Member. Fidus does not represent or pretend to represent Xilinx.

6 Confidential 5 A Hardware Designer's Informal Guide to zynq UltraScale+ Version: 2020-04-06 1 Introduction After delivering more than twenty (20) zynq UltraScale+ ( zynq US+) designs last year, Fidus can truly say that they are expert implementers of the latest Multi-Processor system On-a-Chip ( mpsoc ; pronounced em-pee-sok) technology from Xilinx . These designs spanned multiple applications and markets. This whitepaper is targeted at people who are generally familiar with the zynq US+ and are either, a) Considering zynq US+ for their next design, b) Want to gain insight into some common zynq US+ applications, and/or c) Frankly, potential Customers who are considering Fidus for their next custom zynq US+ design.

7 This paper can also be used as a Guide to the most design critical Xilinx zynq US+ reference documents. I m Scott, a Hardware designer by trade, so this document focuses mostly on the actual Hardware aspects related to zynq US+. And let s face it, a paper on zynq US+ FPGA and Software development would be several thousand pages long as the chip can do pretty much anything. Hope you enjoy and find this article of value. Feel free to reach out via the contact information provided at the end. Confidential 6 A Hardware Designer's Informal Guide to zynq UltraScale+ Version: 2020-04-06 2 The Tips This section describes some of the most valuable knowledge and interesting resources I ve come across when designing with the zynq US+.

8 It is my hope that these little tidbits will help jumpstart your design, or (better yet), give you the full confidence that Fidus is the right partner to get a great zynq US+ design to market fast! Selecting your Device Following on the success of the 7-series zynq device, zynq US+ is the latest mpsoc from Xilinx. The zynq US+ is a heterogenous device consisting of two main elements: A processing system (PS) and a Programmable Logic (PL) system . The PS contains hard elements (meaning elements that cannot be reconfigured like they can be in the PL section) such as ARM Processors and related support architecture, Memory Controllers, a whole slew of Hardware controllers ( SecureDigital, I2C, SPI, USB, PCIe, etc.)

9 , and a variety of other fixed functions. The PL system is the traditional programmable fabric ( FPGA with high-speed I/O and gigabit-rate transceivers) that Xilinx made their name delivering. Provisioning your function correctly by assigning the sub-blocks into either PS or PL is a critical architectural element of designing with zynq US+. Warning! With a chip as flexible and powerful as the zynq US+ it s tempting to haphazardly dive in and just say we ll figure out the provisioning later, but don t do this, sure you may get it to work in the end, but spending the time upfront will pay off in terms of development effort, overall elegance, and hence time-to-market.

10 So, how do I pick my target device? The zynq US+ comes in three different family members: CG, EV, and EG. The following table from Xilinx clearly identifies the functional differences. You will note that the table is entitled processing system Features . You can extrapolate from this that the differences between the CG, EV, and EG, are in the PS (or the hard blocks) and not necessarily within the PL. Ref: #productTable Although not strictly in line with Xilinx marketing lingo, we boil down the differences as follows: CG.