Accelerating Industrialization and remaining challenges ...

1 Accelerating Industrialization and remaining challenges for SiC power devices Thomas NEYER, tech. fellow, SiC Technology ON's status chart for SiC. - Substrate needs - Product releases Diodes: 40000. 4A 50A for 650V available as discretes 35000. alt. sources under 6A 50A for 1200V an in modules 30000. evaluation 25000. Sources secured 20000. MosFET: 15000. Q1/2018: 80m 1200V in TO247 released safe launch 10000. from Q2/2019: 5000. 20m , 40m , 160m in TO247-3L. 0. Q2 same products in D2 PAK-7L, TO247-4L. 2015 2016 2017 2018 2019 2020. - critical substrate supply SiC 6 Volume ramp-up SIC WEEKLY WAFER STARTS. Huge Fab capacity available: > WSPW SBD MosFET Modules Global Development - 24hrs: Asia/EU/US 5,0.

2 4,5. 4,0. 3,5. 3,0. 2,5. 2,0. 1,5. 1,0. 0,5. 0,0. 2015 2016 2017 2018 2019 2020. 3 12/12/2018. Customer projects SiC MosFET - OBC. 40kW on-board rapid charger for E-Bus fleet (36 SiC MosFETs/system). Performance traits: - Excellent current sharing - Good dvdt control (>25V/ns). - Active rectification - zero field fails Customer projects SiC MosFET FormulaE. High performance traction system: 50A Diodes 1200V 160A MosFET (16 in parallel). Overdrive boost (increased VDC, VGS_op). 5 12/12/2018. SiC performance beats Silicon in volume applications Traction system level evaluation: Other system evaluations in ON: 3-phase 10kW OBC/PFC stage Motoring Operation Die Losses (per switch) and 70-140kHz Temperature Peak efficiency: ~99% (limited by inductor).

3 IGBT/Diode 2X8mm2 600 2X15mm2 + 2X10mm2 142 142. 160. 140. 500 117 117. 120. 400. Temperatire, C. Losses, W. 84 84 88 88 100. 81 81. 300 80. 60. 200. 40. 100. 20. Full-bridge DCDC converter (hard switching). 0 Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower 0. IGBT IGBT Diode Diode MOSFET MOSFET MOSFET MOSFET MOSFET MOSFET. SW Loss, W Vin=400V, Vout=220V, Tj=110 C, 13 ARMS. Cond Loss, W Max Temp, C 4xNTHL040N65S3F (650V, SuperFETIII): Peak efficiency: Die 4x60m (900V, SiC MosFET): Peak efficiency: Cond Loss, W SW Loss, W Max Temp, C. 6 12/12/2018. SiC MosFET competitive in Si Super Junction applications Example 900V SiCFET vs 650V SuperJunction FET for LLC.

4 Due to low QOSS, QG and Qrr SiCFET excellent in LLC. 7 12/12/2018. SiC performance beats Silicon IGBTs in the lab FS4-1200V 20A vs. ON Semi SiC MOSFET. Paralleling of 20m ON Semi SiC MosFETs vs IGBTs under identical drive conditions 600V 500A turn on fast SiC turn-on fast SiC turn-off VGE= - 5 / +20V. faster Turn-on Eon at 25 C Eoff at 25 C. current no current tail 8 12/12/2018. challenges limiting factor for scaling Limiting factor for SiC MosFET: Rsp [m .cm2] channel resistance .. Resistance Resistance component percentage Approaches: N+ source %. - Vertical channel (ie Trench) E shielding challenge Channel %. - Deposited GOX intrinsic quality.

5 JFET %. N Epi %. - Low temperature GOX formation - research Sub %. 9 12/12/2018. challenges cooling for small die sizes Real estate for a 60kW 800V DC inverter switch Power dissipation capability [W]. Power density [W/mm2]. 1,6. double 14. side 1,4 direct cooling in scale 12. 1,2. Gen 1: 20%. 10. die area 1. Perfect cooling Increase SiC Tjmax to 200 C. 8. 0,8. Ag sintering Gen 2 single 6. 0,6. side direct cooling Gen 3 0,4 4. 0,2 2. 0 0. Si-IGBT SiC FET 1 SiC FET2 SiC FET 3 Si-IGBT SiC FET 1 SiC FET2 SiC FET 3. challenges - SiC chip in discrete package Large SiC chips in discrete packages FEA modeling discovers: Material Si SiC.

6 Elastic Modulus (Gpa) 130 410. Tensile strength (Mpa) 7000 3440. Hardness (mohs) 9. CTE (1E-6/C) Temperature cycling (-55C 150C). Dependent on chip design, certain locations experience >20 times stress and strain during cycling than Silicon chip Overcame problem with patented design and optimized assembly BOM. 11 12/12/2018. challenges - SiC MosFET in its infancy Typical failure cases for GOX (HTGB burn-in): SiC MosFET in its infancy of volume production (compared to Si), Oxide is thinner and intrinsically less clean Gate oxide integrity for SiC MosFETs and TDDB. In (early) mass production SiC MosFETs need - optimized cleaning, oxidation and anneal EPI defects - Very low electric field (<3 MV/cm) 50%.

7 - tight inline contamination control - highest substrate and Epi quality Failure probability 10%. 5%. Implemented at ON-Semi: 1%. - 100% Epitaxy defect screening - 100% metallic cleaning efficiency - 100% electrical test screening (incl. burn-in) - 100% in-process defect control Bias voltage [V]. challenges - SiC Epitaxy and defectivity control Tracing back burn-in failures to substrate defects Made visible by post Epi scans 14 12/12/2018. challenges - unconstrained supply chain Cost: 30% 30% 15% 12% 13%. external within ON Semi 15 12/12/2018. ON SiC Vertical Integration External boule supply SiC Wafering SiC Epi, Metrology SiC FE Process several sources South Portland, MA, USA.

8 Roznov, Czech Republic and Bucheon, Korea Bucheon, Korea Applications Assembly, test WAT/Sort test Thinning, backmetal Suzhou, China and Seremban, Malaysia Bucheon, Korea Bucheon, Korea Thank You any questions.