AHB Testbench User's Guide - Pulse Logic

1 Verilog AHB TestbenchUser's GuideDocument version: date: March 2010 Pulse : Logic and Electronic SystemsDesign Company Verilog AHB TestbenchTable of Contents1. AHB Bus Testbench Introduction ..32. How To Use This How To Download The Testbench Limitations Of AHB AHBM aster AHBS lave AHBS laveDummy AHBD ecoder AHBA rbiter Module ..1210. AHBM asterToSlave AHBS laveToMaster AHBM asterToArbiter Logic Page: 2 Verilog AHB Testbench1. AHB Bus Testbench Introduction The AHB bus Testbench is written in Verilog-2001 HDL language. All sub modules of the testbenchexcept AHBM aster are synthesizable and can be used for testing and also can be implemented totarget FPGA or ASIC devices. The Testbench is parametrized.

2 It is easy to expand the Testbench andadd more masters or slaves. Each module has parameters allowing quick expansion. Operations ofthe AHB master modules can be customized by defining AHB transfers in a text file. A user mayadd other modules to the Testbench or replace existing modules and test them together to check ifthey correctly respond to different AHB transfers from multiple AHB masters. The Testbench wasdesigned to maximally stress the tested units. All the units must respond in the requested , the bus cycles are always compatible with AMBATM Specification Rev and anydifferences with the specification in timing of the AHB signals should be treated as a bug in thetestbench or in a tested unit. The Testbench consists of the following files:File CodeDefinition of CodeModule for parsing and reading input textfile for AHB RTL code AHB dummy RTL code AHB slave - synchronous RAM RTL code AHB RTL code AHB CodeAHB master bus functional RTL code AHB master to slave multiplexing unit RTL code AHB slave to master multiplexing Obfuscated RTL code AHB master to arbiter multiplexing CodeRTL Top level module connecting all CodeTop level module driving clocks and resetsof all the fileCompilation script fileInput file with AHB transfers definition forMaster fileInput file with AHB transfers definition forMaster filePattern file with responses from Master filePattern file with responses from Master 1.

3 AHB Testbench filesCompilation order and simulation initialization is defined in the file. This is MentorModelsimTM script file format. It can be easy rewritten to Synopsys VCSTM, Cadence NC-SimTM orAldec Active-HDLTM compilation script file. The Testbench consists of the following units: Pulse Logic Page: 3 Verilog AHB Testbench AHBS laveDummy AHBS lave AHBD ecoder AHBA rbiter AHBM aster AHBM asterToSlave AHBS laveToMaster AHBM asterToArbiterFigure 1. Block diagram of AHB TestbenchThe figure above shows interconnections between all the units. The AHB bus does not have anythree-state signals and multiplexing units must be used to connect multiple masters and slaves unit from the figure will be separately described in the following Logic Page: 4 AHBS laveToMasterAHBS laveToMasterAHBM asterAHBM asterToSlaveAHBM asterToSlaveAHBM asterToSlaveAHBD ummySlaveAHBM asterAHBS laveAHBS laveAHBA rbiterAHBM asterToArbiterAHBD ecoderVerilog AHB Testbench2.

4 How To Use This TestbenchThe figure above shows an example of AHB bus system. The system consists of two AHB mastersand two AHB slaves. AHB arbiter is also needed because two masters may access the same slave atthe same time and only one of them can be granted. Similarly, AHB decoder is used to check, whichslave is currently addressed by the granted master. Such system is implemented in The file contains instances of all the mentioned AHB modules connected likein the figure above. More detailed description of all the modules is available in the can run simulation of this system to check how all the modules operate in the system. Scriptfiles and configuration files for AHB masters are provided as mentioned in the previous , remember that all the multiplexing units are highly optimized to avoid any dead cycles onthe bus.

5 The transfers from two masters are parallelized if possible to archive best performance ofthe system. Analyzing the multiplexing units may be difficult. It is much easier to observer interfaceof selected slave or master. Each AHB master writes information about performed transfer to a logfile. The easiest method of analyzing operations of the AHB master is by reviewing the log you are familiar with operation of the Testbench and their modules you can start withmodification of the Testbench architecture. You can do the following: Replace one of existing masters or slaves in the Testbench with yours module Add a new master or slave to the Testbench Change address locations of the AHB slaves Customize input file with transfers definition for AHB mastersThe first three items from the above list can be done by modifications of the can add, remove or replace some instances in the file.

6 If you expand the system by adding moremasters or slaves you must also configure the multiplexing units including AHB arbiter anddecoder. The units have appropriate parameters that needs to be adjusted for given number ofmasters and slaves in the system. More information about parameters of the units is available in thefollowing , customization of the input file with transfers definition for AHB masters is described inthe AHBM aster How To Download The Testbench FilesThe Testbench is available for free under modified BSD license. Click the following link todownload Testbench files: Limitations Of AHB TestbenchThe following functionality was not implemented in the AHB Testbench : Split transfers Retry transfers Early burst terminationThe Testbench is available for free with one limitation.

7 Most of the Testbench files are obfuscated. Itmeans that comments and text formating ware removed from the files and most of identifiers warereplaced with automatically generated strings. It makes the files very difficult to read or , the files are fully functional and should work correctly with any simulation or synthesistool. The original Testbench files are not available for free. Pulse Logic Page: 5 Verilog AHB Testbench5. AHBM aster ModuleThe AHBM aster module implements functionality of AHB master device. It is able to initiatetransfers on AHB bus and write or read data from AHB slaves. The following tables show interfaceof the AHBM aster module:Parameter ValueDescriptionP_IN_FILENAME" " Input file name with definition of bus cyclesP_OUT_FILENAME" "Output log file nameP_MASTER_NAME"master"Master name used for identifying messages from a masterinstanceP_STOP_SIM_AT_EOF1If not equal to '0' the $stop is called when end of input fileis 2.

8 Parameters of AHBM aster modulePort Direction DescriptionHCLKINC lockHRESETnINResetHBUSREQOUTAHB bus requestHLOCKOUTAHB locked transferHGRANTINAHB bus grantHTRANS [1 : 0] OUTAHB transfer type signalHBURST [2 : 0]OUTAHB burst type signalHSIZE [2 : 0] OUTAHB transfer sizeHADDR [31 : 0] OUTAHB address busHPROT [3 : 0] OUTAHB protection controlHWDATA [31 : 0]OUTAHB write data busHWRITEOUTAHB transfer direction signalHRDATA [31 : 0] INAHB read data busHRESP [1 : 0]INAHB transfer response signalHREADYINAHB transfer done signalTable 3. Interface signals of AHBM aster moduleThe AHBM aster module is a typical bus functional model. The AHBM aster reads commands frominput text file defined by P_IN_FILENAME parameter. The input file contains definition of AHBbus transfers that should be generated on the AHB bus. The AHBM aster module records alloperation in a log file specified by P_OUT_FILENAME parameter.

9 It also prints some messages onsimulator console. It is useful to select different name for each master instance usingP_MASTER_NAME parameter. It allows easier identification of messages from given master onsimulator console. Each master may optionally stop simulation if P_STOP_SIM_AT_EOFparameter is set to one. The AHBM aster module calls $stop task after reaching end of input filePulse Logic Page: 6 Verilog AHB Testbenchwhen P_STOP_SIM_AT_EOF parameter equal to interface of AHBM aster module consists of AHB signals. Please, refer to AMBATMS pecification Rev for more details on AHB signals and protocol of user does not need to know functionality of the AHBM aster module.

10 A user may customizeAHBM aster module operation by providing input file with transfers definition. The input file is asimple text file where AHB transfers are defined using very simple format. The design contains twosample input files and that can be used as reference. Below is description ofthe input file are two possible line types in the input file: COMMAND line. Defines AHB transfer that should be generated DATA line. Defines data that should be sent over AHB bus when AHBM aster moduleperforms write transferThe command line starts from COMMAND keyword followed by semicolon and list of parametersdefining AHB transfer. The data line starts from DATA keyword followed by semicolon andhexadecimal data word that should be transferred over AHB bus. Below is an example of commandand data line:COMMAND: WRITE BITS32 SINGLE LENGTH: 0 PROT: 0 ADDRESS: 00000000 BREQ_DELAY: 8 DATA: 00000000 In case of burst transfer the command line must be followed by multiple data lines defining all datawords that must be transferred during the burst cycle.