AHB Testbench User's Guide - Pulse Logic

Verilog AHB TestbenchUser's GuideDocument version: date: March 2010 Pulse : Logic and Electronic SystemsDesign Company Verilog AHB TestbenchTable of Contents1. AHB Bus Testbench Introduction ..32. How To Use This How To Download The Testbench Limitations Of AHB AHBM aster AHBS lave AHBS laveDummy AHBD ecoder AHBA rbiter Module ..1210. AHBM asterToSlave AHBS laveToMaster AHBM asterToArbiter Logic Page: 2 Verilog AHB Testbench1. AHB Bus Testbench Introduction The AHB bus Testbench is written in Verilog-2001 HDL language. All sub modules of the testbenchexcept AHBM aster are synthesizable and can be used for testing and also can be implemented totarget FPGA or ASIC devices. The Testbench is parametrized.

Verilog AHB Testbench 5. AHBMaster Module The AHBMaster module implements functionality of AHB master device. It is able to initiate transfers on AHB bus and write or read data from AHB slaves.

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