ARM Cortex-A53 MPCore Processor

1 Copyright 2013-2014 ARM. All rights DDI 0500D (ID021414)ARM cortex -A53 MPCore ProcessorRevision: r0p2 Technical Reference Manual ARM DDI 0500 DCopyright 2013-2014 ARM. All rights Cortex-A53 MPCore ProcessorTechnical Reference ManualCopyright 2013-2014 ARM. All rights InformationThe following changes have been made to this NoticeWords and logos marked with or are registered trademarks or trademarks of ARM in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright product described in this document is subject to continuous developments and improvements.

2 All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the the term ARM is used it means ARM or any of its subsidiaries as appropriate .Confidentiality StatusThis document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document StatusThe information in this document is final, that is for a developed historyDateIssueConfidentialityChange09 August 2013 AConfidentialRelease for r0p005 November 2013 BConfidentialRelease for r0p110 January 2014 CConfidentialRelease for r0p214 February 2014 DNon-ConfidentialSecond release for r0p2 ARM DDI 0500 DCopyright 2013-2014 ARM.

3 All rights Cortex-A53 MPCore Processor Technical Reference ManualPrefaceAbout this book .. viiFeedback .. xiChapter the Cortex-A53 Processor .. options .. features .. documentation and design flow .. revisions .. 1-12 Chapter 2 Functional the Cortex-A53 Processor functions .. and resets .. management .. 2-16 Chapter 3 Programmers the programmers model .. architecture concepts .. 3-4 Chapter 4 System system control .. 4-2 ContentsARM DDI 0500 DCopyright 2013-2014 ARM. All rights register summary .. register descriptions .. register summary .. register descriptions .. 4-157 Chapter 5 Memory Management the MMU.

4 Organization .. match process .. aborts .. 5-5 Chapter 6 Level 1 Memory the L1 memory system .. behavior .. for v8 memory types .. Instruction memory system .. Data memory system .. prefetching .. access to internal memory .. 6-13 Chapter 7 Level 2 Memory the L2 memory system .. Control Unit .. master interface .. master interface .. memory attributes .. integrated L2 cache .. 7-19 Chapter 8 Cache protection behavior .. reporting .. 8-4 Chapter 9 Generic Interrupt Controller CPU the GIC CPU Interface .. programmers model .. 9-3 Chapter 10 Generic the Generic Timer.

5 Timer functional description .. Timer register summary .. 10-4 Chapter debug .. register interfaces .. debug register summary .. debug register descriptions .. debug register summary .. debug register descriptions .. register summary .. register descriptions .. events .. debug interface .. table .. 11-41 Chapter 12 Performance Monitor the PMU .. functional description .. 12-3 ContentsARM DDI 0500 DCopyright 2013-2014 ARM. All rights PMU register summary .. PMU register descriptions .. PMU register summary .. PMU register descriptions .. register summary .. register descriptions.

6 PMU events .. 12-41 Chapter 13 Embedded Trace the ETM .. trace unit generation options and resources .. trace unit functional description .. of operation and execution .. trace unit register interfaces .. register summary .. register descriptions .. with debug and performance monitoring unit .. 13-76 Chapter 14 Cross the cross trigger .. inputs and outputs .. CTM .. trigger register summary .. trigger register descriptions .. 14-8 Appendix ASignal the signal descriptions .. signals .. signals .. signals .. Interrupt Controller signals .. Timer signals .. management signals.

7 Error signals .. and CHI interface signals .. interface signals .. interface signals .. interface signals .. debug interface .. interface signals .. ETM trace unit signals .. interface signals .. interface signals .. and MBIST interface signals .. A-32 Appendix BCortex-A53 Processor AArch32 unpredictable of R15 by Instruction .. instructions within an IT Block .. accesses crossing page boundaries .. Debug unpredictable behaviors .. unpredictable behaviors .. B-11 Appendix CRevisionsARM DDI 0500 DCopyright 2013-2014 ARM. All rights preface introduces the ARM cortex -A53 MPCore Processor Technical Reference Manual.

8 It contains the following sections: About this book on page vii. Feedback on page ARM DDI 0500 DCopyright 2013-2014 ARM. All rights this bookThis book is for the Cortex-A53 MPCore Processor . This is a cluster device that has between one and four revision statusThe rmpn identifier indicates the revision status of the product described in this book, for example, r1p2, where:rm Identifies the major revision of the product, for example, Identifies the minor revision or modification status of the product, for example, audienceThis book is written for system designers, system integrators, and programmers who are designing or programming a System-on-Chip (SoC) that uses the Cortex-A53 this bookThis book is organized into the following chapters.

9 Chapter 1 Introduction Read this for an introduction to the Cortex-A53 Processor and descriptions of the major 2 Functional Description Read this for a description of the functionality of the Cortex-A53 3 Programmers Model Read this for a description of the programmers 4 System Control Read this for a description of the system registers and programming 5 Memory Management Unit Read this for a description of the Memory Management Unit (MMU).Chapter 6 Level 1 Memory System Read this for a description of the Level 1 (L1) memory 7 Level 2 Memory System Read this for a description of the Level 2 (L2) memory 8 Cache Protection Read this for a description of the cache 9 Generic Interrupt Controller CPU Interface Read this for a description of the Generic Interrupt Controller (GIC) CPU 10 Generic Timer Read this for a description of the Generic ARM DDI 0500 DCopyright 2013-2014 ARM.

10 All rights 11 Debug Read this for a description of the debug registers and shows examples of how to use 12 Performance Monitor Unit Read this for a description of the Performance Monitor Unit (PMU).Chapter 13 Embedded Trace Macrocell Read this for a description of the Embedded Trace Macrocell (ETM) for the Cortex-A53 14 Cross Trigger Read this for a description of the cross trigger A Signal Descriptions Read this for a description of the signals in the Cortex-A53 B Cortex-A53 Processor AArch32 unpredictable Behaviors Read this for a description of specific Cortex-A53 Processor UNPREDICTABLE C Revisions Read this for a description of the technical changes between released issues of this ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms.