ARM1176JZF-S Technical Reference Manual

1 Copyright 2004-2009 ARM Limited. All rights DDI 0301H (ID012310)ARM1176 JZF-S Revision: r0p7 Technical Reference Manual ARM DDI 0301 HCopyright 2004-2009 ARM Limited. All rights , Unrestricted AccessARM1176 JZF-STechnical Reference ManualCopyright 2004-2009 ARM Limited. All rights InformationThe following changes have been made to this NoticeWords and logos marked with or are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith.

2 However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the the term ARM is used it means ARM or any of its subsidiaries as appropriate .Figure 14-1 on page 14-2 reprinted with permission from IEEE Std. , IEEE Standard Test Access Port and Boundary-Scan Architecture by IEEE Std. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described material in this document is based on IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std 754-1985. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described mannerConfidentiality StatusThis document is Non-Confidential.

3 The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document Access is an ARM internal historyDateIssueConfidentialityChange19 July 2004 ANon-ConfidentialFirst April 2005 BNon-ConfidentialMinor corrections and June 2005 CNon-Confidentialr0p1 changes, addition of CPUCLAMPF igure 10-1 23-1 corrections and March 2006 DNon-ConfidentialUpdate for r0p2. Minor corrections and July 2006 ENon-ConfidentialPatch update for April 2007 FNon-ConfidentialUpdate for r0p6 release. Minor corrections and February 2008 GNon-ConfidentialUpdate for r0p7 release. Minor corrections and November 2009 HNon-ConfidentialUpdate for r0p7 maintenance release. Minor corrections and enhancements. ARM DDI 0301 HCopyright 2004-2009 ARM Limited. All rights , Unrestricted AccessProduct StatusThe information in this document is final, that is for a developed DDI 0301 HCopyright 2004-2009 ARM Limited.

4 All rights , Unrestricted AccessContentsARM1176 JZF-S Technical Reference ManualPrefaceAbout this book .. xxiiFeedback .. xxviChapter the processor .. to ARMv6 .. security extensions .. architecture with Jazelle technology .. of the processor .. management .. options .. stages .. pipeline operations .. instruction set summary .. revisions .. 1-47 Chapter 2 Programmer s the programmer s model .. world and Non-secure world operation with TrustZone .. operating states .. length .. types .. formats .. in a processor system .. modes .. program status registers .. instructions .. 2-30 ContentsARM DDI 0301 HCopyright 2004-2009 ARM Limited. All rights , Unrestricted .. considerations .. 2-59 Chapter 3 System Control the system control coprocessor .. control processor registers .. 3-13 Chapter 4 Unaligned and Mixed-endian Data Access unaligned and mixed-endian support.

5 Access support .. support .. of unaligned accesses .. access support .. to reverse bytes in a general-purpose register .. to change the CPSR E bit .. 4-21 Chapter 5 Program Flow program flow prediction .. prediction .. stack .. Barriers .. IMB implementation .. 5-10 Chapter 6 Memory Management the MMU .. organization .. access sequence .. and disabling the MMU .. access control .. region attributes .. attributes and types .. aborts .. fault checking .. status and address .. page table translation .. descriptors .. software-accessible registers .. 6-53 Chapter 7 Level One Memory the level one memory system .. organization .. memory .. and cache interactions .. buffer .. 7-16 Chapter 8 Level Two the level two interface .. primitives .. control signals in the processor .. Fetch Interface transfers .. Read/Write Interface transfers.

6 Interface transfers .. access .. 8-39 Chapter 9 Clocking and clocking and resets .. 9-2 ContentsARM DDI 0301 HCopyright 2004-2009 ARM Limited. All rights , Unrestricted and resets with no IEM .. and resets with IEM .. modes .. 9-10 Chapter 10 Power power control .. management .. shutdown .. Energy Management .. 10-7 Chapter 11 Coprocessor the coprocessor interface .. pipeline .. queue management .. queues .. transfer .. coprocessors .. 11-22 Chapter 12 Vectored Interrupt Controller the PL192 Vectored Interrupt Controller .. the processor VIC port .. of the VIC port .. entry flowchart .. 12-7 Chapter systems .. the debug unit .. registers .. registers reset .. debug instructions .. debug interface .. the debug enable signals .. events .. exception .. state .. communications channel .. in a cached system.

7 In a system with TLBs .. debug-mode debugging .. debug-mode debugging .. signals .. 13-52 Chapter 14 Debug Test Access Test Access Port and Debug state .. RealView ICE .. Debug state .. Debug state .. DBGTAP port and debug registers .. registers .. the Debug Test Access Port .. sequences .. debug events .. debug-mode debugging .. 14-42 Chapter 15 Trace Interface the ETM interface .. 15-2 ContentsARM DDI 0301 HCopyright 2004-2009 ARM Limited. All rights , Unrestricted AccessChapter 16 Cycle Timings and Interlock cycle timings and interlock behavior .. interlock examples .. processing instructions .. , QDADD, QSUB, and QDSUB instructions .. media data-processing .. Sum of Absolute Differences (SAD) .. state updating instructions .. load and store instructions .. and Store Double instructions .. and Store Multiple Instructions .. and SRS instructions.

8 Instructions .. instructions .. , SMC, BKPT, Undefined, and Prefetch Aborted instructions .. operation .. instructions .. 16-28 Chapter 17AC timing diagrams .. timing parameters .. 17-3 Chapter 18 Introduction to the VFP the VFP11 coprocessor .. interface .. coprocessor pipelines .. of operation .. vector instructions .. execution of instructions .. treatment of branch instructions .. optimal VFP11 code .. revision information .. 18-17 Chapter 19 The VFP Register the register file .. file internal formats .. the register file .. operands from ARM11 registers .. consistency in register precision .. transfer between memory and VFP11 registers .. to register banks in CDP operations .. 19-10 Chapter 20 VFP Programmer s the programmer s model .. with the IEEE 754 standard .. coprocessor extensions .. system registers.

9 20-12 Chapter 21 VFP Instruction instruction execution .. instructions .. the VFP11 coprocessor .. of the scoreboards .. hazards in full-compliance mode .. 21-13 ContentsARM DDI 0301 HCopyright 2004-2009 ARM Limited. All rights , Unrestricted hazards in RunFast mode .. hazards .. execution .. timing .. 21-22 Chapter 22 VFP Exception exception processing .. instructions .. code .. processing .. Subnormal exception .. Operation exception .. by Zero exception .. exception .. exception .. exception .. exceptions .. exceptions .. 22-20 Appendix ASignal signals .. configuration signals .. internal signals .. signals, including VIC interface .. interface signals .. interface signals .. interface signals, including JTAG .. interface signals .. signals .. A-16 Appendix BSummary of ARM1136JF-S and ARM1176 JZF-S Processor the differences between the ARM1136JF-S and ARM1176 JZF-S processors.

10 Of differences .. B-3 Appendix CRevisionsGlossaryARM DDI 0301 HCopyright 2004-2009 ARM Limited. All rights , Unrestricted AccessList of TablesARM1176 JZF-S Technical Reference ManualChange history .. iiTable 1-1 TCM configurations .. 1-13 Table 1-2 Double-precision VFP operations .. 1-20 Table 1-3 Flush-to-zero mode .. 1-20 Table 1-4 Configurable options .. 1-25 Table 1-5 ARM1176 JZF-S processor default configurations .. 1-25 Table 1-6 Key to instruction set tables .. 1-32 Table 1-7 ARM instruction set summary .. 1-33 Table 1-8 Addressing mode 2 .. 1-40 Table 1-9 Addressing mode 2P, post-indexed only .. 1-41 Table 1-10 Addressing mode 3 .. 1-42 Table 1-11 Addressing mode 4 .. 1-42 Table 1-12 Addressing mode 5 .. 1-42 Table 1-13 Operand2 .. 1-43 Table 1-14 Fields .. 1-43 Table 1-15 Condition codes .. 1-43 Table 1-16 Thumb instruction set summary .. 1-44 Table 2-1 Write access behavior for system control processor registers.